Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
---|---|---|---|---|---|---|
2010 | A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology | Yen-Chuan Huang; TAI-CHENG LEE | IEEE Journal of Solid-State Circuits | 18 | ||
2011 | A 10-b 400Ms/s 36mW interleaved ADC | Y-C Huang; C-Y Lin; TAI-CHENG LEE | IEEE RFIT Symposium | |||
2011 | A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques | Y-C Huang; TAI-CHENG LEE | IEEE Transactions on Circuits and Systems, Part I | 18 | ||
2010 | A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques | Yen-Chuang Huang; TAI-CHENG LEE | International Solid-State Circuit Conference | |||
2012 | A 10-bit 200-MS/s Reconfigurable Pipelined A/D Converter | C-C Ho; TAI-CHENG LEE | IEEE VLSI DAT | |||
2007 | A 10-Bit Binary-Weighted DAC with Digital Background LMS Calibration | D.-L Shen; Y-C Lai; TAI-CHENG LEE | IEEE Asian Solid-State Circuit Conference | |||
2014 | A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique | C-Y Lin; TAI-CHENG LEE | IEEE Symposium on VLSI Circuits | |||
2001 | A 125-MHz Mixed-Signal Equalizer for Gigabit Ethernet on Copper Wire | TAI-CHENG LEE ; B. Razavi | IEEE Custom Integrated Circuits Conference | |||
2006 | A 14-Gb/s 4-PAM adaptive analog equalizer for 40-inch backplane interconnections | Q.-T. Chen; Y.-C. Huang; TAI-CHENG LEE | Asian Solid-State Circuit Conference (ASSCC) | |||
2014 | A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise | P-C Huang; W-S Chang; TAI-CHENG LEE | International Solid-State Circuit Conference | |||
2014 | A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise | P-C Huang; W-S Chang; TAI-CHENG LEE | IEEE Journal of Solid-State Circuits | |||
2014 | A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator | Y-H Kang; C-Y Lin; TAI-CHENG LEE | IEEE ISCAS | |||
2010 | A 300- to 800-MHz De-Skew Clock Generator for Arbitrary Delay | Y-C Hung; K Fong; TAI-CHENG LEE | IEEE Asian Solid-State Circuit Conference | |||
2010 | A 320-MHz CMOS Continuous-Time ΔΣ Modulator With 5-MHz Signal Bandwidth and 8.3-bit ENOB | K-T Chen; TAI-CHENG LEE | International Journal of Electrical Engineering | |||
2014 | A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth | J-A Cheng; W-S Chang; TAI-CHENG LEE | IEEE VLSI-DAT | |||
2007 | A 4-Channel Poly-Phase Filter for Cognitive Radio Systems | G-J Chen; H-H Chiu; TAI-CHENG LEE | IEEE VLSI-DAT | |||
2008 | A 4-PAM Adaptive Analog Equalizer for Backplane Interconnections | Y-C Huang; Q-T Chen; TAI-CHENG LEE | IEEE VLSI-DAT | |||
2001 | A 4-Tap 125-MHz Mixed-Signal Echo Canceller for Gigabit Ethernet on Copper Wire | TAI-CHENG LEE ; B. Razavi | IEEE Journal of Solid-State Circuits | |||
2005 | A 40-GHz Distributed-Load Static Divider | TAI-CHENG LEE ; etal | IEEE Asian Solid-State Circuit Conference | |||
2006 | A 6-b 1.3Gs/s A/D Converter with C-2C Switch–Capacitor Technique | Y-M Liao; TAI-CHENG LEE | IEEE VLSI-DAT |