公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2012 | Timing ECO optimization using metal-configurable gate-array spare cells | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | Proceedings - Design Automation Conference | 4 | 0 | |
2012 | Timing ECO optimization via B?zier curve smoothing and fixability identification | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 11 | 9 | |
2011 | Timing ECO optimization via B?zier curve smoothing and fixability identification | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design | 2 | 0 | |
2018 | Timing Macro Modeling for Efficient Hierarchical Timing Analysis. | Jiang, Iris Hui-Ru; Lee, Pei-Yu; HUI-RU JIANG | 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018 | | | |
2022 | Timing macro modeling with graph neural networks | Chang, Kevin Kai Chun; Chiang, Chun Yao; Lee, Pei Yu; HUI-RU JIANG | Proceedings - Design Automation Conference | 3 | 0 | |
2008 | Topology generation and floorplanning for low power application-specific network-on-chips | Lee, W.-Y.; HUI-RU JIANG | 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT | | | |
2008 | Unification of obstacle-avoiding rectilinear steiner tree construction | Jiang, I.H.-R.; Lin, S.-W.; Yu, Y.-T.; HUI-RU JIANG | 2008 IEEE International SOC Conference, SOCC | | | |
2009 | VIFI-CMP: Variability-tolerant chip-multiprocessors for throughput and power | Lee, W.Y.; HUI-RU JIANG | Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI | | | |
2012 | WiT: Optimal wiring topology for electromigration avoidance | Chang, H.-Y.; Chang, C.-L.; HUI-RU JIANG | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 21 | 19 | |