公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2008 | Calibrating Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signals, Sensors, and Systems Test Workshop | 6 | 0 | |
2009 | Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC Input | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | Asia and South Pacific Design Automatic Conference | |||
2009 | Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC | X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 1 | 0 | |
2015 | Design and Implementation of an FPGA-Based Data/Timing Formatter | Y.-Y. Chen; J.-L. Huang; T. Kuo; X.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 6 | 6 | |
2014 | FPGA-Based Subset Sum Delay Lines | C.-Y. Wang; Y.-Y. Chen; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2012 | Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications | Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium |