Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
---|---|---|---|---|---|---|
2014 | FPGA-Based Subset Sum Delay Lines | C.-Y. Wang; Y.-Y. Chen; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2012 | Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications | Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium |