| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2017 | A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer with an Adaptation Time of 2.68 μs | Chen, K.-Y.; Chen, W.-Y.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 8 | 7 | |
| 2017 | A 0.31-pJ/bit 20-Gb/s DFE with 1 Discrete Tap and 2 IIR Filters Feedback in 40-nm-LP CMOS | Chen, K.-Y.; Chen, W.-Y.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 15 | 16 | |
| 2015 | A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS | Hsieh, C.-E.; Liu, S.-I.; SHEN-IUAN LIU | Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 | 14 | 0 | |
| 2015 | A 0.43pJ/bit true random number generator | Kuan, T.-K.; Chiang, Y.-H.; Liu, S.-I.; SHEN-IUAN LIU | Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 | 21 | 0 | |
| 2002 | A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture | Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan | 2002 IEEE Asia-Pacific Conference on ASIC | 2 | 0 |  |
| 2007 | A 1.2-V 37-38.5-GHz eight-phase clock generator in 0.13-μm CMOS technology | Cho, L.-C.; Lee, C.; Liu, S.-I.; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 39 | 31 | |
| 2020 | A 1.22 mW 2.4 GHz PLL Using a Single-Ring-Oscillator-Based Integrator with Background Frequency Calibration | Su G.-Y; Liu S.-I.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems I: Regular Papers | 4 | 3 | |
| 2009 | A 1.5 GHz all-digital spread-spectrum clock generator | Lin, S.-Y.; Liu, S.-I.; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 56 | 44 | |
| 2016 | A 10-20 Gb/s CDR circuit with 6200ppm frequency tracking | Huang, C.-C.; Tseng, K.-W.; SHEN-IUAN LIU | RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology | 0 | 0 | |
| 2016 | A 10-bit 40-MS/s Time-Domain Two-Step ADC with Short Calibration Time | Chen, L.-J.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 12 | 14 | |
| 2009 | A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology (vol 56, pg 97, 2009) | Lu, Jian-Hao; Chen, Ke-Hou; Liu, Shen-Iuan; SHEN-IUAN LIU | Ieee Transactions on Circuits and Systems Ii-Express Briefs | 2 | 0 | |
| 2006 | 10GBase-LX CMOS automatic gain control amplifier design | Wang, I.-H.; Chen, W.-S.; Liu, S.-I.; SHEN-IUAN LIU | 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005 | 4 | 0 | |
| 2007 | 10GBase-T乙太網路系統晶片設計－子計畫四：適用於10GBase-T乙太網路接收機之類比數位轉換電路(2/3) | 劉深淵 | | | | |
| 2007 | 10GBase-T乙太網路系統晶片設計－子計畫四：適用於10GBase-T乙太網路接收機之類比數位轉換電路(3/3) | 劉深淵 | | | | |
| 2008 | 10GBase-T乙太網路系統晶片設計－總計畫(2/3) | 劉深淵 | | | | |
| 2007 | 10GBase-T乙太網路系統晶片設計－總計畫(3/3) | 劉深淵 | | | | |
| 2008 | 10Gbps inductorless CDRs with digital frequency calibration | Che-Fu Liang; Hong-Lin Chu; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems I: Regular Papers | 12 | 11 | |
| 2016 | A 12-bit 3.4 MS/s two-step cyclic time-domain ADC in 0.18-μm CMOS | Chen, L.-J.; Liu, S.-I.; SHEN-IUAN LIU | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 15 | 13 | |
| 2019 | A 13.4-MHz Relaxation Oscillator With Temperature Compensation | Chang, Yi-An; Liu, Shen-Iuan; SHEN-IUAN LIU | Ieee Transactions on Very Large Scale Integration (vlsi) Systems | 18 | 15 | |
| 2018 | A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control | Luo, Y.-S.; Lin, H.-H.; Liu, S.-I.; SHEN-IUAN LIU | 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings | 0 | 0 | |
