| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2006 | A 0.18μm probabilistic-based noise-tolerate circuit design and implementation with 28.7dB noise-immunity improvement | Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 | 22 | 0 | |
| 2004 | 1000BASE-T Gigabit Ethernet baseband DSP IC design | Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | | |  |
| 2008 | 10GBase-T乙太網路系統晶片設計－子計畫五：適用於10GBase-T乙太網路之高效能數位信號處理引擎設計(2/3) | 吳安宇 | | | | |
| 2007 | 10GBase-T乙太網路系統晶片設計－子計畫五：適用於10GBase-T乙太網路之高效能數位信號處理引擎設計(3/3) | 吳安宇 | | | | |
| 2003 | 2002 IEEE 信號系統研討會 | 吳安宇 | | | | |
| 2019 | A 232-1996-kS/s robust compressive sensing reconstruction engine for real-time physiological signals monitoring | Chen, Ting Sheng; HUNG-CHI KUO ; AN-YEU(ANDY) WU | IEEE Journal of Solid-State Circuits | 9 | 9 | |
| 2018 | A 232-to-1996KS/s Robust Compressive-Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring | Ting-Sheng Chen; Hung-Chi Kuo; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE International Solid-State Circuits Conference (ISSCC) | 9 | 0 | |
| 2021 | A 7.8-13.6 pJ/b Ultra-Low latency and reconfigurable neural network-assisted polar decoder with multi-code length support | AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems I: Regular Papers | 2 | 1 | |
| 2008 | An 8.29mm2 52mW Multi-mode LDPC Decoder Design for Mobile WiMAX System in 0.13um CMOS Process | Xin-Yu Shih; Cheng-Zhou Zhan; Cheng-Hung Lin; An-Yeu Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Journal of Solid-State Circuits | 109 | 91 | |
| 0 | a | a; AN-YEU(ANDY) WU ; 吳安宇 | | | | |
| 2007 | A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement | Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2007 IEEE Asian Solid-State Circuits Conference | 3 | 0 | |
| 2011 | A 0.16nJ/bit/iteration 3.38mm 2 turbo decoder chip for WiMAX/LTE standards | Lin, C.-H.; Chen, C.-Y.; Chang, E.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2011 International Symposium on Integrated Circuits | 8 | 0 | |
| 2015 | A 1.96 mm 2 low-latency multi-mode crypto-coprocessor for PKC-based IoT security protocols | CR Tsai; MC Hsiao; WC Shen; AYA Wu; CM Cheng; CHEN-MOU CHENG ; AN-YEU(ANDY) WU | 2015 IEEE International Symposium on Circuits and Systems (ISCAS) | 3 | 0 | |
| 2007 | A 19-mode 8.29mm2 52-mW LDPC decoder chip for IEEE 802.16e system | Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Symposium on VLSI Circuits | 17 | 0 | |
| 2010 | A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system | Chen, Y.-L.; Jheng, T.-J.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU | ESSCIRC 2010 - 36th European Solid State Circuits Conference | 0 | 0 | |
| 2005 | A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications | Wey, I.-C.; Chang, L.-H.; Chen, Y.-G.; Chang, S.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 4 | 0 | |
| 2009 | A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications | Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | Asia and South Pacific Design Automation Conference, ASP-DAC | 1 | 0 | |
| 2008 | A 7.39mm2 76mw (1944, 972) LDPC decoder chip for IEEE 802.11n applications | Shih, X.-Y.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 | 12 | 0 | |
| 2009 | A channel-adaptive early termination strategy for LDPC decoders | Chen, Y.-H.; Chen, Y.-J.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 9 | 0 | |
| 2007 | A clock-fault tolerant architecture and circuit for reliable nanoelectronics system | Ang, W.T.; Rao, H.F.; Yu, C.; Liu, J.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; Chen, J.; AN-YEU(ANDY) WU | 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007 | 6 | 0 | |
