公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2010 | 3D-PIC: An Error Tolerant 3D CMOS Imager | H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG | 3D Integration Workshop | |||
2002 | A BIST Scheme for the Embedded ADC in ADSL SoC | Y. J. Chang; S. J. Chang; C. K. Ong; J. C. Ho; J. L. Huang; K. T. Cheng; W. C. Wu; JIUN-LANG HUANG | VLSI Design/CAD Symposium | |||
2008 | A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays | C.-W. Lin; Jiun-Lang Huang; JIUN-LANG HUANG | VLSI Test Symposium | 11 | 0 | |
2013 | A circular pipeline processing based deterministic parallel test pattern generator | K.-W. Yeh; J.-L. Huang; H.-J. Chao; L.-T. Wang; JIUN-LANG HUANG | International Test Conference | 9 | 0 | |
2003 | A Delay-Line Based On-Chip Jitter Measurement Technique | J. J. Huang; J. L. Huang; JIUN-LANG HUANG | VLSI Design/CAD Symposium | |||
2009 | A DfT Technique for Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input | X.-L. Huang; C.-Y. Yang; J.-L. Huang; JIUN-LANG HUANG | International Journal of Electrical Engineering | |||
2005 | A Fabrication Process Variation Based Approach to Evaluate Design-for-Test Techniques | Y. R. Chen; J. L. Huang; JIUN-LANG HUANG | Bulletin of the College of Engineering | |||
2012 | A fault-tolerant PE array based matrix multiplier design | B.-Y. Jan; J.-L. Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 0 | 0 | |
2009 | A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method | K.-W. Yeh; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | International Conference on Algorithms and Architectures for Parallel Processing | 10 | 0 | |
2007 | A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing | T.-L. Hung; J.-L. Huang; JIUN-LANG HUANG | VLSI Test Symposium | 2 | 0 | |
2013 | A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers | H.-M. Chang; J.-L. Huang; D.-M. Kwai; K.-T. Cheng; C.-W. Wu; JIUN-LANG HUANG | IEEE Transactions on Very Large Scale Integration | 6 | 6 | |
2006 | A low-cost jitter measurement technique for BIST applications | JIUN-LANG HUANG ; J.-J. Huang; Y.-S. Liu | Journal of Electronic Testing: Theory and Applications (JETTA) | 6 | 4 | |
2003 | A low-cost jitter measurement technique for BIST applications | J. J. Huang; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 18 | 4 | |
2013 | A mutual characterization based SAR ADC self-testing technique | H.-J. Lin; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | European Test Symposium | 5 | 0 | |
2006 | A period tracking based on-chip sinusoidal jitter extraction technique | C.-Y. Kuo; JIUN-LANG HUANG | Proceedings of the IEEE VLSI Test Symposium | 8 | 0 | |
2011 | A pre- and post-bond self-testing and calibration methodology for SAR ADC Array in 3-D Imager | X.-L. Huang; P.-Y. Kang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; JIUN-LANG HUANG | European Test Symposium | 5 | 0 | |
2006 | A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter | J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 6 | 0 | |
2006 | A routability constrained scan chain ordering technique for test power reduction | X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | Asia and South Pacific Design Automation Conference | 8 | ||
2012 | A SAR ADC missing-decision level detection and removal technique | X.-L. Huang; J.-L. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG | VLSI Test Symposium | 0 | 0 | |
2010 | A scalable quantitative measure of IR-drop for scan pattern generation | M.-F. Wu; K.-H. Tsai; W.-T. Cheng; H.-C. Pan; J.-L. Huang; A. Kifli; JIUN-LANG HUANG | International Conference on Computer-Aided Design | 4 | 0 |