| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2012 | 3D IC test scheduling using simulated annealing | CY Hsu; CY Kuo; JCM Li; K. Chakrbarty; CHIEN-MO LI | IEEE VLSI-DAT | 6 | 0 | |
| 2004 | A Design for Testability Technique for Low Power Delay Fault Testing | Li, J. C. M.; CHIEN-MO LI | IEICE Transactions on Electronics | 3 | 4 | |
| 2008 | A Dual-rail Asynchronous Scan Chain Design and Its Implementation in TFT Technology | C. H. Cheng; J. C.M. Li; CHIEN-MO LI | VLSI/CAD | | | |
| 2014 | A Flexible TFT Circuit Yield Optimizer Considering Process Variation, Aging, and Bending Effects | Wen-En Wei; Hung-Yi Li; Cheng-Yu Han; James Chien-Mo Li; Jian-Jang Huang; I-Chun Cheng; Chien-Nan Liu; Yung-Hui Yeh; I-CHUN CHENG ; JIAN-JANG HUANG ; CHIEN-MO LI | Journal of Display Technology | 5 | 2 | |
| 2011 | A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives | Liao, Kuan-Yu; Chang, Chia-Yuan; Li, James Chien-Mo; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 14 | 12 | |
| 2012 | A Secure Test Wrapper Design against Internal and Boundary Scan Attacks for Embedded Cores | G.M. Chiu; J. C. M. Li; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 56 | 42 | |
| 2005 | A Two-level Test Data Compression and Test Time Reduction Technique for SOC | Yu-Te Liaw; James C.-M. Li; CHIEN-MO LI | VLSI/CAD Symposium | | | |
| 2011 | An accurate timing-aware diagnosis algorithm for multiple small delay defects | Chen, P.-J.; Hsu, W.-L.; Li, J.C.-M.; Tseng, N.-H.; Chen, K.-Y.; Changchien, W.-P.; Liu, C.C.C.; WEI-LI HSU; CHIEN-MO LI | Asian Test Symposium | 6 | 0 | |
| 2011 | An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology | C. H. Cheng; J. C. M. Li; CHIEN-MO LI | Journal of Electronic Testing | 7 | 7 | |
| 2008 | An Asynchronous DFT Technique for TFT Macroelectronics | C. H. Cheng; C.-H. Hsu; J. C.M. Li; CHIEN-MO LI | International Symposium on Flexible Electronics and Display (ISFED) | | | |
| 2011 | An At-speed Self-testable Technique for the High Speed Domino Adder | Y. Wang; M. Hsieh; C. Liu; C. Liu; J. C.-M. Li; C.-P. Chen; CHIEN-MO LI | IEEE CICC poster | 1 | 0 | |
| 2012 | An At-speed Test Technique for High-speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example | Y. S. Wang; M. H. Hsieh; J. C. M. Li; C. C. P. Chen; CHIEN-MO LI | IEEE Transactions on Circuits and Systems I: Regular Papers | 2 | 2 | |
| 1998 | Analysis of pattern-dependent and timing-dependent failures in an experimental test chip. | Chang, Jonathan T.-Y.; Tseng, Chao-Wen; Li, Chien-Mo James; Purtell, Mike; McCluskey, Edward J.; CHIEN-MO LI | Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998 | 0 | 0 | |
| 2019 | ATPG and test compression for probabilistic circuits | Yang, K.-C.; Lee, M.-T.; Wu, C.-H.; Li, J.C.-M.; CHIEN-MO LI | 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 | 1 | 0 | |
| 2020 | Automatic IR-Drop ECO Using Machine Learning | Lin H.-Y; Fang Y.-C; Liu S.-T; Chen J.-X; Li C.-M; Fang E.J.-W.; CHIEN-MO LI | Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 | 4 | 0 | |
| 2017 | Automatic test pattern generation | Cheng, K.-T.T.; Wang, L.-C.; Li, H.; Li, J.C.-M.; CHIEN-MO LI | Electronic Design Automation for IC System Design, Verification, and Testing | 2 | 0 | |
| 2013 | Automatic Test Pattern Generation for Delay Defects Using Timed Characteristic Functions | Shin-Yann Ho; Shuo-Ren Lin; Ko-Lung Yuan; Chien-Yen Kuo; Kuan-Yu Liao; Jie-Hong Rol Jiang; Chien-Mo Li; CHIEN-MO LI | Int’l Conf. on CAD | 2 | 0 | |
| 2013 | Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM | BC Bai; C-L Hsu; MH Wu; CA Chen; YW Chen; KL Luo; LC Cheng; JCM Li; CHIEN-MO LI | IEEE Asian Test Symposium | 2 | 0 | |
| 2009 | BIST Design Optimization for Large-Scale Embedded Memory Cores | T.-F. Chien; W.-C. Chao; J. C.-M. Li; K.-Y. Liao; Y.-W. Chang; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; CHIEN-MO LI | 2009 International Conference on Computer-Aided Design | 7 | 0 | |
| 2009 | Bridging Fault Diagnosis to Identify the Layer of Systematic Defects | B. R. Chen; J. C.M. Li; CHIEN-MO LI | Asian Test Symposium | 3 | 0 | |
