公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2005 | A 1.2V 6.7mW impulse-radio UWB baseband transceiver | CHIA-HSIANG YANG ; Yang, C.-H.; Chen, K.-H.; Chiueh, T.-D.; CHIA-HSIANG YANG | IEEE International Solid-State Circuits Conference | | | |
2013 | A 191μW BPSK demodulator for data and power telemetry in biomedical implants | CHIA-HSIANG YANG ; Wang, L.-L.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG | ACM Great Lakes Symposium on VLSI, GLSVLSI | | | |
2009 | A 2.89mW 50GOPS 16 × 16 16-core MIMO sphere decoder in 90nm CMOS | CHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | ESSCIRC 2009 - 35th European Solid-State Circuits Conference | | | |
2013 | A 28.6μW mixed-signal processor for epileptic seizure detection | CHIA-HSIANG YANG ; Chen, T.-J.; Lee, S.-C.; Yang, C.-H.; Chiu, C.-F.; Chiueh, H.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | | | |
2014 | A 5.4 μw soft-decision bch decoder for wireless body area networks | CHIA-HSIANG YANG ; Yang, C.-H.; Huang, T.-Y.; Li, M.-R.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | | | |
2010 | A 5.8mW 3GPP-LTE compliant 8×8 MIMO sphere decoder chip with soft-outputs | CHIA-HSIANG YANG ; Yang, C.-H.; Yu, T.-H.; Marković, D.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | | | |
2012 | A 7.4-mW 200-MS/s wideband spectrum sensing digital baseband processor for cognitive radios | CHIA-HSIANG YANG ; Yu, T.-H.; Yang, C.-H.; Čabrić, D.; Marković, D.; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | | | |
2011 | A 7.4mW 200MS/s wideband spectrum sensing digital baseband processor for cognitive radios | CHIA-HSIANG YANG ; Yu, T.-H.; Yang, C.-H.; Čabrić, D.; Marković, D.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | | | |
2011 | A 75μW, 16-channel neural spike-sorting processor with unsupervised clustering | Karkare, Vaibhav; Gibson, Sarah; CHIA-HSIANG YANG ; Chen, Henry; Marković, Dejan | IEEE Symposium on VLSI Circuits | | | |
2015 | A 794Mbps 135mW iterative detection and decoding receiver for 4x4 LDPC-coded MIMO systems in 40nm | CHIA-HSIANG YANG ; Wu, W.-H.; Sun, W.-C.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | | | |
2016 | A 98.6μW acoustic signal processor for fully-implantable cochlear implants | Liu, H.-M.; Lin, Y.-J.; Lee, Y.-C.; Lee, C.-Y.; CHIA-HSIANG YANG | 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 | | | |
2009 | A flexible DSP architecture for MIMO sphere decoding | CHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | | | |
2008 | A flexible VLSI architecture for extracting diversity and spatial multiplexing gains in MIMO channels | CHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | IEEE International Conference on Communications | | | |
2014 | A fully integrated 8-channel closed-loop neural-prosthetic cmos soc for real-time epileptic seizure control | CHIA-HSIANG YANG et al. | IEEE Journal of Solid-State Circuits | 183 | 162 | |
2013 | A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control | CHIA-HSIANG YANG | IEEE International Solid-State Circuits Conference | | | |
2015 | A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia | CHIA-HSIANG YANG | IEEE Transactions on Biomedical Circuits and Systems | | | |
2014 | A fully parallel ldpc decoder architecture using probabilistic min-sum algorithm for high-throughput applications | CHIA-HSIANG YANG ; Cheng, C.-C.; Yang, J.-D.; Lee, H.-C.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | | | |
2011 | A hardware-efficient VLSI architecture for hybrid sphere-MCMC detection | CHIA-HSIANG YANG ; Yuan, F.-L.; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | GLOBECOM - IEEE Global Telecommunications Conference | | | |
2013 | A hierarchical approach for online temporal lobe seizure detection in long-term intracranial EEG recordings | CHIA-HSIANG YANG ; Liang, S.-F.; Chen, Y.-C.; Wang, Y.-L.; Chen, P.-T.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG | Journal of Neural Engineering | | | |
2008 | A multi-core sphere decoder VLSI architecture for MIMO communications | CHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | GLOBECOM - IEEE Global Telecommunications Conference | | | |