| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2012 | A chip-package-board co-design methodology | Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 4 | 0 | |
| 2011 | A corner stitching compliant B-tree representation and its applications to analog placement | Tsao, H.-F.; Chou, P.-Y.; Huang, S.-L.; Chang, Y.-W.; Lin, M.P.-H.; Chen, D.-P.; Liu, D.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 23 | 0 | |
| 2003 | A fast crosstalk- and performance-driven multilevel routing system | Ho, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-Jie ; Lee, D.T. | IEEE/ACM International Conference on Computer-Aided Design | 0 | 0 |  |
| 2003 | A Fast Crosstalk- and Performance-Driven Multilevel Routing System | Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.T.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 46 | | |
| 2006 | A high-quality mixed-size analytical placer considering preplaced blocks and density constraints | Chen, T.-C.; Jiang, Z.-W.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 62 | 0 | |
| 2007 | A network-flow-based RDL routing algorithmz for flip-chip design | Fang, J.-W.; Lin, I.-J.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 59 | 44 | |
| 2014 | A new asynchronous pipeline template for power and performance optimization | Ho, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 8 | 0 | |
| 2007 | A new interference phenomenon in sub-60nm nitride-based flash memory | Chang, Y.W.; YAO-WEN CHANG et al. | 22nd IEEE Non-Volatile Semiconductor Memory Workshop | 5 | 0 | |
| 2008 | A new multilevel framework for large-scale interconnect-driven floorplanning | Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 28 | 24 | |
| 2006 | A novel framework for multilevel full-chip gridless routing | Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 14 | | |
| 2002 | A novel framework for multilevel routing considering routability and performance | Lin, S.-P.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 55 | 0 | |
| 2009 | A novel hot-electron programming method in a buried diffusion bit-line SONOS memory by utilizing nonequilibrium charge transport | Wang, T.; Tang, C.-J.; Li, C.-W.; Lee, C.-H.; Ou, T.-F.; Chang, Y.-W.; Tsai, W.-J.; Lu, T.-C.; Chen, K.-C.; Lu, C.-Y.; YAO-WEN CHANG | IEEE Electron Device Letters | 0 | 0 | |
| 2014 | A novel layout decomposition algorithm for triple patterning lithography | Fang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 46 | 43 | |
| 2012 | A novel layout decomposition algorithm for triple patterning lithography | Fang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG | Design Automation Conference | 47 | 0 | |
| 2009 | A novel wire-density-driven full-chip routing system for cmp variation control | Chen, H.-Y.; Chou, S.-J.; Wang, S.-L.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 23 | 21 | |
| 2008 | A progressive-ILP based routing algorithm for cross-referencing biochips | Yuh, Ping-Hung; Sapatnekar, S.; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG ; CHIA-LIN YANG | Design Automation Conference | 69 | 0 | |
| 2009 | A progressive-ILP-based routing algorithm for the synthesis of cross-referencing biochips | Yuh, P.-H.; Sapatnekar, S.S.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG ; CHIA-LIN YANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2 | 5 | |
| 2004 | A reusable methodology for non-slicing floorplanning | Hsu, J.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS | 1 | | |
| 2005 | A routing algorithm for flip-chip design | Fang, J.-W.; Lin, I.-J.; Yuh, P.-H.; Wang, J.-H.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 43 | 0 | |
| 2007 | A statistical approach to the timing-yield optimization of pipeline circuits | Hsu, C.-H.; Chou, S.-J.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG | Lecture Notes in Computer Science | 0 | | |
