| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2016 | Fast lithographic mask optimization considering process variation | Su, Y.-H.; Huang, Y.-C.; Tsai, L.-C.; Chang, Y.-W.; Banerjee, S.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 34 | 30 | |
| 2015 | Fast lithographic mask optimization considering process variation | Su, Y.-H.; Huang, Y.-C.; Tsai, L.-C.; Chang, Y.-W.; Banerjee, S.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 9 | 0 | |
| 1996 | Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation | Chen, Chung-Ping; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG | Design Automation Conference | 24 | | |
| 1996 | Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. | Chen, Chung-Ping; Chang, Yao-Wen; Wong, D. F.; YAO-WEN CHANG | Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996. | 24 | 0 | |
| 2012 | Fast timing-model independent buffered clock-tree synthesis | Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 14 | 10 | |
| 2010 | Fast timing-model independent buffered clock-tree synthesis | Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 23 | 0 | |
| 2009 | Flip-chip routing with unified area-I/O pad assignments for package-board co-design. | Fang, Jia-Wei; Wong, Martin D. F.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 39 | 0 | |
| 2006 | Floorplan and power/ground network co-synthesis for fast design convergence | Liu, C.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 22 | | |
| 2006 | Floorplan and power/ground network co-synthesis for fast design convergence. | Liu, Chen-Wei; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006 | 22 | 0 | |
| 2009 | Floorplanning | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | Electronic Design Automation | 5 | 0 | |
| 2017 | Fogging Effect Aware Placement in Electron Beam Lithography | Huang, Y.-C.; Chang, Y.-W. | Design Automation Conference | 7 | 0 | |
| 2015 | Foreword | Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 0 | 0 | |
| 2002 | Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. | Chang, Nicholas Chia-Yuan; Chang, Yao-Wen; YAO-WEN CHANG ; HUI-RU JIANG | 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002 | 1 | 0 | |
| 1995 | FPGA global routing based on a new congestion metric | Wong, D.F.; Wong, C.K.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 13 | | |
| 2017 | FPGA placement and routing | Chen, S.-C.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 16 | 0 | |
| 2007 | Full-Chip Nanometer Routing Techniques. | Ho, Tsung-Yi; Chang, Yao-Wen; Chen, Sao-Jie; YAO-WEN CHANG | | | | |
| 2008 | Full-chip routing considering double-via insertion | Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 61 | 46 | |
| 2008 | Full-Chip Routing Considering Double-Via Insertion | Chen, Huang-Yu; Chiang, Mei-Fang; Chang, Yao-Wen ; Chen, Lumdo; Han, B. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | 46 |  |
| 2014 | Functional ECO using metal-configurable gate-array spare cells | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | Design Automation Conference | 1 | 0 | |
| 2018 | Generalized augmented lagrangian and its applications to VLSI global placement | Zhu, Z.; Chen, J.; Peng, Z.; Zhu, W.; Chang, Y.-W. | Design Automation Conference | 15 | 0 | |
