| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2005 | Joint exploration of architectural and physical design spaces with thermal consideration. | Wu, Yen-Wei; Yang, Chia-Lin; Yuh, Ping-Hung; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005 | 18 | 0 | |
| 2020 | Latch clustering for timing-power co-optimization | Huang, C.-C.; Tellez, G.; Nam, G.-J.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 2 | 0 | |
| 2023 | Late Breaking Results: An Efficient Bridge-based Compression Algorithm for Topologically Quantum Error Corrected Circuits | Tseng, Wei Hsiang; YAO-WEN CHANG | Proceedings - Design Automation Conference | | | |
| 2023 | Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies | Chen, Yan Jen; Chen, Yan Syuan; Tseng, Wei Che; Chiang, Cheng Yu; Lo, Yu Hsiang; YAO-WEN CHANG | Proceedings - Design Automation Conference | | | |
| 2022 | Late Breaking Results: Flexible Chip Placement via Reinforcement Learning | Chang, Fu Chieh; Tseng, Yu Wei; Yu, Ya Wen; Lee, Ssu Rui; Cioba, Alexandru; Tseng, I. Lun; Shiu, Da Shan; Hsu, Jhih Wei; Wang, Cheng Yuan; Yang, Chien Yi; Wang, Ren Chu; YAO-WEN CHANG ; Chen, Tai Chen; Chen, Tung Chieh | Proceedings - Design Automation Conference | 0 | | |
| 2022 | Late Breaking Results: Subgraph Matching Based Reference Placement for PCB Designs | Su, Miaodi; Xiao, Yifeng; Zhang, Shu; Su, Haiyuan; Xu, Jiacen; He, Huan; Zhu, Ziran; Chen, Jianli; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | | |
| 2013 | Layer minimization in escape routing for staggered-pin-array PCBs | Ho, Y.-K.; Shih, X.-W.; Chang, Y.-W.; Cheng, C.-K.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 5 | 0 | |
| 2015 | Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning | Fang, S.-Y.; Tai, Y.-S.; Chang, Y.-W.; YAO-WEN CHANG | 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 | 7 | 0 | |
| 2004 | Layout techniques for on-chip interconnect inductance reduction | Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 1 | | |
| 2004 | Layout techniques for on-chip interconnect inductance reduction. | Tu, Shang-Wei; Jou, Jing-Yang; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |
| 2016 | Layout-Dependent Effects-Aware Analytical Analog Placement | Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 44 | 37 | |
| 2015 | Layout-dependent-effects-aware analytical analog placement | Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 15 | 0 | |
| 2019 | Many-body theory of optical absorption in doped two-dimensional semiconductors | Chang, Y.-W.; Reichman, D.R.; YAO-WEN CHANG | Physical Review B | 25 | 22 | |
| 2023 | A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints | Liu, Qinghai; Lin, Disi; Chen, Chuandong; He, Huan; Chen, Jianli; YAO-WEN CHANG | Proceedings - Design Automation Conference | | | |
| 2001 | Matching-Based Algorithm for FPGA Channel Segmentation Design | YAO-WEN CHANG ; Lin, Jai-Ming; Wong, M. D. F. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 6 | 6 |  |
| 2012 | Material characterization of polycarbonate near glass transition temperature | JUNG-HO CHENG ; YAO-WEN CHANG | Journal of the Chinese Institute of Engineers, Series A/Chung-kuo Kung Ch'eng Hsuch K'an | 2 | 2 | |
| 1998 | Maximally routable switch matrices for FPD design | Wu, Guang-Min; Chang, Yao-Wen; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 0 | | |
| 2007 | MB*-tree: A multilevel floorplanner for large-scale building-module design | Lee, H.-C.; Chang, Y.-W.; Yang, H.H.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 2 | |
| 2007 | MB^*-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design | Lee, Hsun-Cheng; Chang, Yao-Wen ; Yang, Hannah Honghua | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | | |
| 2019 | MDP-trees: Multi-Domain Macro Placement for Ultra Large-Scale Mixed-Size Designs | Y. C. Liu; T. C. Chen; Y. W. Chang; S. Y. Kuo; Chang, Y.-W. | 24th Asia and South Pacific Design Automation Conference (ASP-DAC 2019) | 3 | 0 | |
