| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2017 | Nanowire-Aware Routing Considering High Cut Mask Complexity | Su, Y.-H.; Chang, Y.-W. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 0 | |
| 2015 | Nanowire-aware routing considering high cut mask complexity | Su, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 11 | 0 | |
| 2012 | Native-conflict and stitch-aware wire perturbation for double patterning technology | Fang, S.-Y.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 20 | 16 | |
| 2010 | Native-conflict-aware wire perturbation for double patterning technology | Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 23 | 0 | |
| 2007 | A Network-Flow-Based RDL Routing Algorithm for Flip-Chip Design | Fang, Jia-Wei; Lin, I-Jye; Chang, Yao-Wen ; Wang, Jyh-Herng | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | |  |
| 1994 | New global routing algorithm for FPGAs | Chang, Yao-Wen; Thakur, Shashidhar; Zhu, Kai; Wong, D.F.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | | |
| 1994 | A new global routing algorithm for FPGAs. | Chang, Yao-Wen; Thakur, Shashidhar; Zhu, Kai; Wong, D. F.; YAO-WEN CHANG | Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994 | 0 | 0 | |
| 2008 | A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning | Chen, Tung-Chieh; Chang, Yao-Wen ; Lin, Shyh-Chang | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | 24 | |
| 2003 | Noise-aware buffer planning for interconnect-driven floorplanning | Li, S.-M.; Cherng, Y.-H.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 6 | 0 | |
| 1999 | Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. | Jiang, Iris Hui-Ru; Jou, Jing-Yang; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999. | 9 | 0 | |
| 2015 | Non-stitch triple patterning-aware routing based on conflict graph pre-coloring | Hsu, P.-Y.; Chang, Y.-W.; YAO-WEN CHANG | 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 | 8 | 0 | |
| 2012 | Non-uniform multilevel analog routing with matching constraints | Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 24 | 0 | |
| 2014 | Nonuniform multilevel analog routing with matching constraints | Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 22 | 17 | |
| 2017 | A novel damped-wave framework for macro placement | Chang, C.-H.; Chang, Y.-W. ; Chen, T.-C. | IEEE/ACM International Conference on Computer-Aided Design | 11 | 0 | |
| 2006 | A novel framework for multilevel full-chip gridless routing | Chen, Tai-Chen; Chang, Yao-Wen ; Lin, Shyh-Chang | Asia and South Pacific Conference on Design Automation, 2006. | 0 | 0 | |
| 2006 | Novel Full-Chip Gridless Routing Considering Double-Via Insertion | Chen, Huang-Yu; Chiang, Mei-Fang; Chang, Yao-Wen ; Chen, Lumdo; Han, Brian | | | |  |
| 2006 | Novel full-chip gridless routing considering double-via insertion | Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG | Design Automation Conference | 31 | 0 | |
| 2018 | Novel proximal group ADMM for placement considering fogging and proximity effects | Chen, J.; Yang, L.; Peng, Z.; Zhu, W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 8 | 0 | |
| 2007 | Novel wire density driven full-chip routing for CMP variation control | Chen, H.-Y.; Chou, S.-J.; Wang, S.-L.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 16 | 0 | |
| 2018 | NTU place4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs with Technology and Region Constraints | Huang, C.-C.; Lee, H.-Y.; Lin, B.-Q.; Yang, S.-W.; Chang, C.-H.; Chen, S.-T.; Chang, Y.-W. ; Chen, T.-C.; Bustany, I. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 34 | 31 | |
