公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2009 | Performance-energy tradeoffs in reliable NoCs | Lan, Y.-C.; Chen, M.C.; Chen, W.-D.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | 10th International Symposium on Quality Electronic Design, ISQED 2009 | 5 | 0 | |
2009 | Pilot study on a community-based ubiquitous healthcare system for current and retired university employees | Su, M.-J.; Zhang, H.-W.; Lin, Y.-J.; Su, Y.-H.; Chen, S.-J.; Chen, H.-S.; SAO-JIE CHEN | 2009 IEEE International Conference on Communications Workshops, ICC 2009 | 6 | 0 | |
1992 | Planar Moat Routing | Tsai, C. C.; 陳少傑 ; Chen, Sao-Jie | 3rd Workshop on CAD for VLSI | | | |
1996 | Planar routing in a pin grid array package | Tsai, Chia-Chun; Chen, Sao-Jie; SAO-JIE CHEN | Journal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an | | | |
1993 | Planar Routing on a Pin Grid Array Package | Tsai, C. C.; 陳少傑 ; Chen, Sao-Jie | 1993 Third International Conference on CAD & CG | | | |
1992 | Planning Strategies for Area Routing | Tsai, C. C.; 陳少傑 ; Chen, Y. L.; Hu, Y. H.; Chen, Sao-Jie | 1992 European Conference on Design Automation | | | |
2020 | A Platform of Resynthesizing a Clock Architecture into Power-and-Area Effective Clock Trees | Lin, T.-L.; Chen, S.-J.; SAO-JIE CHEN | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 2 | |
2002 | Printed circuit board routing and package layout codesign | Chen, S.-S.; Tseng, W.-D.; Yan, J.-T.; Chen, S.-J.; SAO-JIE CHEN | IEEE Asia-Pacific Conference on Circuits and Systems | 9 | 0 | |
1996 | PSM: An object-oriented synthesis approach to multiprocessor system design | Hsiung, P.-A.; Chen, S.-J.; Hu, T.-C.; Wang, S.-C.; SAO-JIE CHEN | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 16 | 14 | |
2010 | QoS aware BiNoC architecture | Lo, S.-H.; Lan, Y.-C.; Yeh, H.-H.; Tsai, W.-C.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | 2010 IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010 | 15 | 0 | |
2011 | Rate-allocation for spatially scalable video coding | Peng, G.-J.; Hwang, W.-L.; Chen, S.-J.; SAO-JIE CHEN | ISPA 2011 - 7th International Symposium on Image and Signal Processing and Analysis | | | |
2005 | Real-time implementation of noise-immune gradient-based edge detection | Hsiao, P.-Y.; Wen, H.; Chen, Y.-P.; Chen, S.-J.; SAO-JIE CHEN | ISSCS 2005: International Symposium on Signals, Circuits and Systems | 4 | 0 | |
2006 | Real-time realisation of noise-immune gradient-based edge detector | Hsiao, P.-Y.; Chen, C.-H.; Wen, H.; SAO-JIE CHEN | IEE Proceedings: Computers and Digital Techniques | 13 | 7 | |
2012 | Reconfigurable networks-on-chip | Chen, S.-J.; Lan, Y.-C.; Tsai, W.-C.; Hu, Y.-H.; SAO-JIE CHEN | Reconfigurable Networks-on-Chip | 11 | 0 | |
1994 | Reflexive Object-Oriented Software Engineering | Hsu, F. M.; See, W. B.; Fuh, R. M.; 陳少傑 ; Chen, Sao-Jie | Fourth Workshop on Object-Oriented Technology | | | |
2023 | A Robust Super-Regenerative Receiver with Optimal Detection on BER Level | Su, Yi Pei; Huang, Chao Yen; SAO-JIE CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | 0 | 0 | |
1991 | Routing Area Compaction Based On Iterative Construction | Tsai, C.-C.; Chen, S.-J.; Hsiao, P.-Y.; Feng, W.-S.; SAO-JIE CHEN | Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an | 0 | 0 | |
1994 | A Routing System for the PGA Package | Wang, C. M.; Tsai, C. C.; 陳少傑 ; Chen, Sao-Jie | 5th VLSI Design/CAD Symposium | | | |
1990 | Routing Techniques in Staircase Channels | Fang, S. C.; 陳少傑 ; 馮武雄; Chen, Sao-Jie ; Feng, Wu-Shiung | 1990 2nd Workshop on CAD for VLSI | | | |
1994 | Row-Based and Symmetrical Field Programmable Gate Arrays Routing | Chen, J. Y.; 陳少傑 ; Ho, J. M.; Chen, Sao-Jie | 5th VLSI Design/CAD Symposium | | | |