公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
1994 | A Routing System for the PGA Package | Wang, C. M.; Tsai, C. C.; 陳少傑 ; Chen, Sao-Jie | 5th VLSI Design/CAD Symposium | | | |
1990 | Routing Techniques in Staircase Channels | Fang, S. C.; 陳少傑 ; 馮武雄; Chen, Sao-Jie ; Feng, Wu-Shiung | 1990 2nd Workshop on CAD for VLSI | | | |
1994 | Row-Based and Symmetrical Field Programmable Gate Arrays Routing | Chen, J. Y.; 陳少傑 ; Ho, J. M.; Chen, Sao-Jie | 5th VLSI Design/CAD Symposium | | | |
1994 | Scheduling algorithm for nonpreemptive multiprocessor tasks | Lin, J.-F.; SAO-JIE CHEN | Computers and Mathematics with Applications | 13 | 10 | |
1994 | Scheduling parallel tasks on hypercubes | Lin, J.-F.; SAO-JIE CHEN | Electronics Letters | 0 | 0 | |
1994 | Scheduling Parallel Tasks With Setup Time on Hypercube Systems | Lin, J. F.; See, W. B.; 陳少傑 ; Chen, Sao-Jie | International Computer Symposium | | | |
2009 | Simdcode generation for multimedia applications | Lin, G.-H.; Wen, Y.-N.; Wu, X.-L.; Chen, S.-J.; Su, A.P.; SAO-JIE CHEN | International Journal of Electrical Engineering | | | |
2003 | Simultaneous routing and buffering in floorplan design | Fang, J.P.; Tong, Y.-S.; SAO-JIE CHEN | International Symposium on VLSI Technology, Systems, and Applications | 1 | 0 | |
2004 | Simultaneous routing and buffering in SOC floorplan design | Fang, J.P.; Tong, Y.-S.; SAO-JIE CHEN | IEE Proceedings: Computers and Digital Techniques | 5 | 5 | |
2004 | Software platform for embedded software development | See, W.-B.; Hsiung, P.-A.; Lee, T.-Y.; Chen, S.-J.; SAO-JIE CHEN | Lecture Notes in Computer Science | | | |
1996 | A stable partitioning algorithm for VLSI circuits | Cherng, Jong-Sheng; Chen, Sao-Jie | Custom Integrated Circuits Conference, 1996. | 0 | 0 | |
1996 | Stable partitioning algorithm for VLSI circuits | Cherng, Jong-Sheng; Chen, Sao-Jie; SAO-JIE CHEN | Custom Integrated Circuits Conference | | | |
2007 | Symbolic verification and error prediction methodology | Wei, C.-J.; Lin, G.-H.; Wen, Y.-N.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | 20th Anniversary IEEE International SOC Conference | 0 | 0 | |
2001 | Symmetric and programmable multi-chip module for low-power prototyping system | Yen, M.-H.; Chen, S.-J.; Lan, S.H.; SAO-JIE CHEN | VLSI Design | | | |
1999 | Symmetric and programmable multi-chip module for rapid prototyping system | Yen, Mao-Hsu; Chen, Sao-Jie; Lan, Sanko H.; SAO-JIE CHEN | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | | | |
2002 | TCN: Scalable hierarchical hypercubes | Lee, T.-Y.; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN | International Conference on Parallel and Distributed Systems - ICPADS | 1 | 0 | |
2015 | Temporal and spatial denoising of depth maps | Lin, B.-S.; Su, M.-J.; Cheng, P.-H.; Tseng, P.-J.; SAO-JIE CHEN | Sensors (Switzerland) | 15 | 13 | |
2003 | Tile-based power planning during floorplanning | Fang, J.P.; SAO-JIE CHEN | IEEE International SOC Conference, SOCC 2003 | 0 | 0 | |
2003 | Tile-graph-based power planning | Fang, Jyh-Perng; Chen, Sao-Jie | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
2010 | TM-FAR: Turn-model based fully adaptive routing for networks on chip | Tsai, W.-C.; Chu, K.-C.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010 | 8 | 0 | |