公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
1991 | GEAR: a general area router using planning approach | Chen, Yuh-Lin; SAO-JIE CHEN ; Tsai, Chia-Chun; Hu, Yu-Hen | International Symposium on VLSI Technology, Systems, and Applications, Proceedings | 0 | 0 | |
1994 | General area router based on planning techniques | SAO-JIE CHEN ; Tsai, C.-C.; Chen, Y.-L.; Hu, Y.-H. | IEE Proceedings: Computers and Digital Techniques | 0 | 0 | |
1989 | Generalized Terminal Connectivity Problem for Multi-Layer Layout Scheme | Tsai, C. C.; 馮武雄; 陳少傑 ; Hsiao, P, Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie | 1989 Joint Technical Conference on Circuits/Systems, Computers and Communications | | | |
1990 | Generalized terminal connectivity problem for multilayer layout scheme | Tsai, C.-C.; SAO-JIE CHEN ; Feng, W.-S. | Computer-Aided Design | 1 | 0 | |
1989 | GM Plan: A gate matrix layout algorithm based on artificial intelligence planning techniques | SAO-JIE CHEN | IEEE International Symposium on Circuits and Systems | | | |
1990 | GM-Learn: an iterative learning algorithm for CMOS gate matrix layout | Chen, Sao-Jie ; Hu, Yu Hen | IEE Proceedings E: Computers and Digital Techniques | | | |
1989 | GM-Learn:an Iterative Learning Algorithm for CMOS Gate Matrix Layout | 陳少傑 ; Hu, Y. H.; Chen, Sao-Jie | 1989 International Symposium on Circuits and Systems | | | |
1989 | GM_Learn: an iterative learning algorithm for CMOS gate matrix layout | Chen, Sao-Jie ; Hu, Yu Hen | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
1990 | GM_Plan: A Gate Matrix Layout Algorithm Based on Artificial Intelligence Planning Techniques | Hu, Y.H.; Chen, S.-J.; SAO-JIE CHEN | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 17 | 15 | |
1989 | An H-V Tile-Expansion Router | Tsai, C. C.; 陳少傑 ; 馮武雄; Chen, Sao-Jie ; Feng, Wu-Shiung | National Computer Symposium | | | |
2000 | Hard ware-software timing co-verification of distributed embedded systems | Jih-Ming, F.U.; Lee Trong-Yen; Hsiung, P.-A.; SAO-JIE CHEN | IEICE Transactions on Information and Systems | 10 | | |
2015 | Hardware implementation of a real-time distributed video decoder | Yang, H.-P.; Ho, M.-H.; Hsieh, H.-C.; Cheng, P.-H.; Chen, S.-J.; SAO-JIE CHEN | International Conference on Digital Signal Processing, DSP | 1 | 0 | |
2009 | Hardware software co-design of a multimedia SOC platform | Hu, Yu-Hen; Hsiung, Pao-Ann; Lin, Guang-Huei; Chen, Sao-Jie | | 0 | 0 | |
2001 | Hardware-software multi-level partitioning for distributed embedded multiprocessor systems | Lee, T.-Y.; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | | | |
2006 | A healthcare pattern collection for rural telemedicine services | Cheng P.-H.; Shyu M.-F.; SAO-JIE CHEN ; Lai F.; JER-JUNN LUH ; Chen H.-S.; JIN-SHIN LAI | HEALTHCOM 2006: Mobile E-Health for Developing Countries - 2006 8th International Conference on e-Health Networking, Applications and Services | | | |
1997 | Hmap: A fast mapper for EPGAs using extended GBDD hash tables | Yang, C.-H.; Tsai, C.-C.; Ho, J.M.; Chen, S.-J.; SAO-JIE CHEN | ACM Transactions on Design Automation of Electronic Systems | | | |
1991 | Hybrid Routing on Multi-Chip Modules | Tsai, C. C.; 陳少傑 ; Hsiao, P. Y.; 馮武雄; Chen, Sao-Jie ; Feng, Wu-Shiung | 1991 Custom Integrated Circuits Conference | | | |
1991 | Hybrid routing on multichip modules | Tsai, Chia-Chun; Chen, Sao-Jie ; Hsiao, Pei-Yung; Feng, Wu-Shiung | Custom Integrated Circuits Conference | 0 | 0 | |
1998 | ICOS: An intelligent concurrent objectoriented synthesis methodology for multiprocessor systems | Hsiung, P.-A.; Chen, C.-H.; Lee, T.-Y.; SAO-JIE CHEN | ACM Transactions on Design Automation of Electronic Systems | 8 | 0 | |
2002 | IETQ: An incrementally extensible twisted cube | Chang, J.-S.; Chen, S.-J.; Chiueh, T.-D.; SAO-JIE CHEN | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | | | |