公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2013 | Back-Gate Bias Effect of PD SOI NMOS Device Considering BJT | D. H. Lung; J. B. Kuo; JAMES-B KUO | International Conference on EECS | | | |
2014 | Back-Gate-Baias Induced Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device | S. K. Hu; D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO | IEDMS | | | |
1999 | Bandgap Narrowing | JAMES-B KUO | Wiley Encyclopedia on Electrical Engineering | | | |
1993 | A BiCMOS dynamic divider circuit using a nonrestoring iterative architecture with carry look ahead for CPU VLSI | Kuo, J.B.; Chen, H.P.; Huang, H.J.; KuoJB | IEEE International Symposium on Circuits and Systems, 1993. ISCAS '93 | 0 | 0 | |
1992 | A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture | Liao, H.J.; Chen, H.P.; KuoJB | Bipolar/BiCMOS Circuits and Technology Meeting, 1992. | 3 | 0 | |
1992 | BiCMOS dynamic Manchester carry look ahead circuit for high speed arithmetic unit VLSI | Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB | Electronics Letters | | | |
1993 | BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers | Chen S.S; Chiang C.S; Su K.W; JAMES-B KUO | Electronics Letters | 4 | 2 | |
1994 | A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit | Su, K.W.; Lou, J.H.; KuoJB | IEEE International Symposium on Circuits and Systems, 1994. ISCAS '94 | 5 | 0 | |
1991 | BiCMOS edge detector with correlated-double-sampling readout circuit for pattern recognition neural network | Kuo, J.B.; Chou, T.L.; Wong, E.J.; KuoJB | Electronics Letters | | | |
1991 | A BiCMOS tristate buffer for high-speed microprocessor VLSI | Kuo, J.B.; Liao, H.J.; KuoJB | Fourth Annual IEEE International ASIC Conference and Exhibit, 1991 | 0 | 0 | |
1992 | BICMOS元件電路模擬器 | 郭正邦 ; Kao, James B. | | | | |
1992 | BICMOS元件電路混合式模擬器 | 郭正邦 ; Kao, James B. | | | | |
1991 | BiCMOS元件/電路模擬器 | 郭正邦 | | | | |
1990 | BICMOS模擬器 | 郭正邦 ; Kao, James B. | | | | |
2008 | Breakdown Behavior of 40-nm PD-SOI NMOS Device Considering STI-Induced Mechanical Stress Effect | I. S. Lin; V. C. Su; D. Chen; C. S. Yeh; C. T. Tsai; M. Ma; JAMES-B KUO | IEEE Electron Device Letters | 7 | 3 | |
2006 | Capacitance Behavior of Nanometer FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Gate Tunneling Leakage Current | JAMES-B KUO | MIEL | | | |
2011 | Cell-based leakage power reduction priority (CBLPRP) optimization methodology for designing SOC applications using MTCMOS technique | S. F. Huang; R. S. Shen; J. B. Kuo; JAMES-B KUO | Power and Timing Modeling Optimization Symposium | 2 | 0 | |
2005 | CGS Capacitance Phenomenon of 100nm FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Vertical and Fringing Displacement Effects | Y. S. Lin; C. H. Lin; J. B. Kuo; K. W. Su; JAMES-B KUO | HKEDSSC | 0 | 0 | |
2010 | Charge Pumping Behavior of STI-Isolated PD SOI NMOS Device Operating at Low Temp | C. F. Yen; J. B. Kuo; JAMES-B KUO | IEDMS | | | |
2002 | Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion | S. C. Lin; J. B. Kuo; JAMES-B KUO | IEEE Transactions on Electron Devices | 3 | 1 | |