公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2022 | D-NAT: Data-Driven Non-Ideality Aware Training Framework for Fabricated Computing-In-Memory Macros | Lin M.-G; Huang C.-T; Chuang Y.-C; Chen Y.-T; Hsu Y.-T; Chen Y.-K; Chou J.-J; TSUNG-TE LIU ; CHI-SHENG SHIH ; AN-YEU(ANDY) WU | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | 2 | 2 | |
2008 | Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits | I-Chyn Wey; You-Gang Chen; An-Yeu Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 7 | 3 | |
2008 | Design and analysis of isolated noise-tolerant (INT) technique in dynamic CMOS circuits | Wey, I.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 7 | 3 | |
2009 | Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits | Wey, I-Chyn; Chen, You-Gang; Yu, Chang-Hong; Wu, An-Yeu ; Chen, Jie | IEEE Transactions on Circuits and Systems I: Regular Papers | | | |
2009 | Design and Implementation of Cost-Efficient Probabilistic-Based Noise-Tolerant VLSI Circuits | I-Chyn Wey; You-Gang Chen; Chang-Hong Yu; An-Yeu Wu; Jie Chen; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transactions onCircuits and Systems Part-I: Regular Papers | 29 | 21 | |
2004 | A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. | Jheng, Kai-Yuan; Jou, Shyh-Jye; Wu, An-Yeu; AN-YEU(ANDY) WU | Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004 | | | |
2000 | Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem | Leu, Jye-Jong; Wu, An-Yeu; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2000 | Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem. | Leu, Jye-Jong; Wu, An-Yeu; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings | 11 | 0 | |
2013 | Design of thermal management unit with vertical throttling scheme for proactive thermal-aware 3D NoC systems | Chen, K.-C.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2013 International Symposium on VLSI Design, Automation, and Test | 10 | 0 | |
2011 | Design of transport layer assisted routing for thermal-aware 3D Network-on-Chip | Yin, T.-C.; Chao, C.-H.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | APSIPA ASC 2011 - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference 2011 | | | |
2005 | Digital signal processing engine design for polar transmitter in wireless communication systems | Ko, H.-Y.; Wang, Y.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 3 | 0 | |
2006 | DSP engine design for LINC wireless transmitter systems | Jheng, K.-Y.; Wang, Y.-C.; Wu, A.-Y.; Tsao, H.-W.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2006 | DSP engine design for LINC wireless transmitter systems. | Jheng, Kai-Yuan; Wang, Yi-Chiuan; Wu, An-Yeu; HEN-WAI TSAO ; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece | 0 | 0 | |
2003 | Dual-mode convolutional/SOVA based turbo code decoder VLSI design for wireless communication systems | Chen, P.-H.; Kai-Huang; Hsueh, N.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International SOC Conference, SOCC 2003 | 2 | 0 | |
2013 | Dual-mode low-complexity codebook searching algorithm and VLSI architecture for LTE/LTE-advanced systems | Lin, Y.-H.; Chen, Y.-H.; Chu, C.-Y.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Signal Processing | 11 | 8 | |
2013 | Dual-Mode Low-Complexity Codebook Searching Algorithm and VLSI Architecture for LTE/LTE-Advanced Systems | Yi-Hsuan Lin; Yu-Hao Chen; Chun-Yuan Chu; Cheng-Zhou Zhan; An-Yeu Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transactions on Signal Processing (TSP) | 11 | 8 | |
2007 | Dynamic channel flow control of networks-on-chip systems for high buffer efficiency | Wu, S.-T.; Chao, C.-H.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 8 | 0 | |
2015 | Dynamic group allocation reconstruction for group sparse signals | Tu, Y.-M.; Chang, M.C.; Lin, Y.-M.; Wu, A.-Y.A.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
2020 | Dynamic Hyperdimensional Computing for Improving Accuracy-Energy Efficiency Trade-Offs | AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | | | |
2016 | Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing | Ting-Sheng Chen; Ding-Yuan Lee; Tsung-Te Liu; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I) | 26 | 20 | |