公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2022 | FACE RECOGNITION FOR FISHEYE IMAGES | Lo, Yi Cheng; Huang, Chiao Chun; Tsai, Yueh Feng; Lo, I. Chan; AN-YEU(ANDY) WU ; HOMER H. CHEN | Proceedings - International Conference on Image Processing, ICIP | 1 | 0 | |
1998 | Fast algorithm for reduced-complexity programmable DSP implementation of the IFFT/FFT in DMT systems | AN-YEU(ANDY) WU ; Wu, An-Yeu; Chan, Tsun-Shan; Wang, Bowen; AN-YEU(ANDY) WU | IEEE Global Telecommunications Conference | | | |
2004 | Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique | AN-YEU(ANDY) WU ; Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | | | |
2004 | Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique | Meng-Da Yang; An-Yeu Wu; Jyh-Ting Lai; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transaction on Circuits and Systems Part II: Analog and Digital Signal Processing | 3 | 3 | |
2009 | Fault-tolerant Router with Built-in Self-test/Self-diagnosis and Fault-isolation Circuits for 2D-mesh Based Chip Multiprocessor | Lin, Shu-Yen ; Shen, Wen-Chung; Hsu, Chan-Cheng; Wu, An-Yeu | International Journal of Electrical Engineering | | | |
2009 | Fault-tolerant Router with Built-in Self-test/Self-diagnosis and Fault-isolation Circuits for 2D-mesh Based Chip Multiprocessor | Shu-Yen Lin; Wen-Chung Shen; Chan-Cheng Hsu; An-Yeu Wu; AN-YEU(ANDY) WU | International Journal of Electrical Engineering | 21 | 0 | |
2009 | Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2d-mesh based chip multiprocessor systems | AN-YEU(ANDY) WU ; Lin, S.-Y.; Shen, W.-C.; Hsu, C.-C.; AN-YEU(ANDY) WU | International Journal of Electrical Engineering | | | |
2019 | Feature Selection Framework for XGBoost Based on Electrodermal Activity in Stress Detection | AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | | | |
1995 | FFT VLSI Implementation VLSI Signal Processing | 吳安宇 | | | | |
2016 | Filter-based dual-voltage architecture for low-power long-word TCAM design | Chen, T.-S.; Lee, D.-Y.; Liu, T.-T.; AN-YEU(ANDY) WU ; TSUNG-TE LIU | Proceedings of the 2nd International Conference on Intelligent Green Building and Smart Grid, IGBSG 2016 | 4 | 0 | |
2021 | FL-HDC: Hyperdimensional Computing Design for the Application of Federated Learning | AN-YEU(ANDY) WU | 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021 | | | |
2012 | Foreword | AN-YEU(ANDY) WU ; Wu, A.-Y.; Wang, L.-C.; AN-YEU(ANDY) WU | 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 | | | |
2006 | A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time | Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
2010 | Generalized pipelined Tomlinson - Harashima precoder design methodology with build-in arbitrary speed-up factors | AN-YEU(ANDY) WU ; Chen, Y.-L.; AN-YEU(ANDY) WU | IEEE Transactions on Signal Processing | | | |
2010 | Generalized Pipelined Tomlinson–Harashima Precoder Design Methodology With Build-In Arbitrary Speed-Up Factors | Yen-Liang Chen; An-Yeu Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transaction on Signal Processing | 4 | 4 | |
2015 | High performance adaptive routing for Network-on-Chip systems with express highway mechanism | AN-YEU(ANDY) WU ; Lin, S.-C.; Chang, E.-J.; Chen, Y.-Y.; Hsin, H.-K.; AN-YEU(ANDY) WU | IEEE Asia-Pacific Conference on Circuits and Systems | | | |
2009 | High-convergence-speed low-computation-complexity SVD algorithm for MIMO-OFDM systems | AN-YEU(ANDY) WU ; Zhan, C.-Z.; Jheng, K.-Y.; Chen, Y.-L.; Jheng, T.-J.; AN-YEU(ANDY) WU | 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 | | | |
2002 | High-performance adaptive decision feedback equalizer based on predictive parallel branch slicer scheme | Yang, Meng-Da; Wu, An-Yeu | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
2008 | High-performance scheduling algorithm for partially parallel LDPC decoder | AN-YEU(ANDY) WU ; Zhan, C.-Z.; Shih, X.-Y.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | | | |
2004 | High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme | Meng-Da Yang; An-Yeu Wu; Jyh-Ting (Justin) Lai; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 3 | 3 | |