公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2009 | PAC Duo SoC performance analysis with ESL design methodology | Chuang, I.-Y.; Chang, C.-W.; Fan, T.-Y.; Yeh, J.-C.; Ji, K.-M.; Ma, J.-L.; Wu, A.-Y.; Lin, S.-Y.; AN-YEU(ANDY) WU | ASICON 2009 - 8th IEEE International Conference on ASIC | 4 | 0 | |
2011 | Parallel architecture core (PAC)-the first multicore application processor SoC in Taiwan part I: Hardware architecture & software development tools | Chang, D.C.-W.; Lin, T.-J.; Wu, C.-J.; Lee, J.-K.; Chu, Y.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | Journal of Signal Processing Systems | 13 | 6 | |
2011 | Parallel architecture core (PAC)-the first multicore application processor SoC in Taiwan part II: Application programming | Chen, J.-M.; Liu, C.-N.; Yang, J.-K.; Tseng, S.-Y.; Shih, W.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU | Journal of Signal Processing Systems | 4 | 3 | |
1996 | Parallel programmable video co-processor design | Wu, An-Yeu; Ray Liu, K.J.; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU | IEEE International Conference on Image Processing | | | |
1995 | Parallel programmable video co-processor design. | Wu, An-Yeu; Liu, K. J. Ray; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU | Proceedings 1995 International Conference on Image Processing, Washington, DC, USA, October 23-26, 1995 | 0 | 0 | |
2014 | Path-Congestion-Aware Adaptive Routing with a Contention Prediction Scheme for Network-on-Chip Systems | Chang, En-Jui; Hsin, Hsien-Kai; Lin, Shu-Yen; AN-YEU(ANDY) WU ; SHU-YEN LIN | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 56 | 39 | |
2014 | Path-Congestion-Aware Adaptive Routing with a Contention Prediction Scheme for Network-on-Chip Systems | En-Jui Chang; Hsien-Kai Hsin; Shu-Yen Lin; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) | 56 | 38 | |
2012 | Path-diversity-aware adaptive routing in network-on-chip systems | Kuo, Y.-H.; Tsai, P.-A.; Ho, H.-P.; Chang, E.-J.; Hsin, H.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE 6th International Symposium on Embedded Multicore SoCs, MCSoC 2012 | 18 | 0 | |
2017 | Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems | Yu-Yin Chen; En-Jui Chang; Hsien-Kai Hsin; Kun-Chih Chen; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transactions on Parallel and Distributed Systems (TPDS) | 54 | 40 | |
2018 | Polar Feature based Deep Architecture for Automatic Modulation Classification Considering Channel Fading | Chieh-Fang Teng; Ching-Chun Liao; Chun-Hsiang Chen; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Global Conference on Signal and Information Processing (GlobalSIP’18) | 17 | 0 | |
2019 | Polar feature based deep architectures for automatic modulation classification considering channel fading | AN-YEU(ANDY) WU | 2018 IEEE Global Conference on Signal and Information Processing, GlobalSIP 2018 - Proceedings | 17 | 0 | |
2005 | Polar transmitter for wireless communication system | Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai ; Jheng, Kai-Yuan; Wu, An-Yeu | 2005 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2005 | 0 | 0 | |
2006 | A portable all-digital pulsewidth control loop for SOC applications | Wang, Wei; Wey, I-Chyn; Wu, Chia-Tsun; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
2008 | Power efficient low latency survivor memory architecture for viterbi decoder | Chu, C.-Y.; Huang, Y.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT | 10 | 0 | |
2007 | A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance. | Chao, Chih-Hao; Kuo, Yen-Lin; Wu, An-Yeu; Chien, Weber; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA | 0 | 0 | |
2012 | Power-Efficient State Exchange Scheme for Low Latency SMU Design of Viterbi Decoder | Chun-Yuan Chu; AN-YEU(ANDY) WU | Journal of Signal Processing Systems (JSPS) | 3 | 1 | |
2021 | PQ-HDC: Projection-Based Quantization Scheme for Flexible and Efficient Hyperdimensional Computing | AN-YEU(ANDY) WU | IFIP Advances in Information and Communication Technology | 0 | 0 | |
2015 | Predicting stroke outcomes based on multi-modal analysis of physiological signals | Huang, Pei-Wen; SUNG-CHUN TANG ; Lin, Yu-Min; Liu, You-Cheng; Jou, Wei-Jung; Jen, Hsiao-I; DAR-MING LAI ; AN-YEU(ANDY) WU | International Conference on Digital Signal Processing, DSP | 0 | 0 | |
2013 | Proactive thermal-budget-based beltway routing algorithm for thermal-aware 3D NoC systems | Kuo, C.-C.; Chen, K.-C.; Chang, E.-J.; Wu, A.-Y.A.; AN-YEU(ANDY) WU | 2013 International Symposium on System-on-Chip, SoC 2013 | 17 | 0 | |
2013 | Proactive Thermal-Budget-Based Beltway Routing algorithm for thermal-aware 3D NoC systems. | Kuo, Che-Chuan; Chen, Kun-Chih; Chang, En-Jui; Wu, An-Yeu; AN-YEU(ANDY) WU | 2013 International Symposium on System on Chip, ISSoC 2013, Tampere, Finland, October 23-24, 2013 | 12 | 0 | |