公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2009 | A predictive shutdown technique for GPU shader processors | CHIA-LIN YANG ; Wang, Po-Han; Chen, Yen-Ming; Yang, Chia-Lin; Cheng, Yu-Jung; CHIA-LIN YANG | IEEE Computer Architecture Letters | | | |
2008 | A progressive-ILP based routing algorithm for cross-referencing biochips | Yuh, Ping-Hung; Sapatnekar, S.; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG ; CHIA-LIN YANG | Design Automation Conference | 69 | 0 | |
2009 | A progressive-ILP-based routing algorithm for the synthesis of cross-referencing biochips | Yuh, P.-H.; Sapatnekar, S.S.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG ; CHIA-LIN YANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2 | 5 | |
2018 | Active forwarding: Eliminate IOMMU address translation for accelerator-rich architectures | Fu, H.-C.; Wang, P.-H.; CHIA-LIN YANG | Proceedings - Design Automation Conference | 1 | 0 | |
2012 | Age-based PCM wear leveling with nearly zero search cost. | Chen, Chi-Hao; Hsiu, Pi-Cheng; Kuo, Tei-Wei; Yang, Chia-Lin; TEI-WEI KUO ; CHIA-LIN YANG | The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 | 85 | 0 | |
2010 | An analytical model to exploit memory task scheduling | CHIA-LIN YANG ; Cheng, H.-Y.; Li, J.; CHIA-LIN YANG | Annual Workshop on Interaction between Compilers and Computer Architectures | | | |
2009 | An Architectural Co-Synthesis Algorithm for Energy-Aware Network-on-Chip Design | Chen, Yi-Jung; Yang, Chia-Lin ; Chang, Yen-Sheng | Journal of Systems Architecture | 12 | 10 | |
2017 | Analyzing opencl 2.0 workloads using a heterogeneous CPU-GPU simulator | Wang, L.; Tsai, R.-W.; Wang, S.-C.; Chen, K.-C.; Wang, P.-H.; Cheng, H.-Y.; Lee, Y.-C.; Shu, S.-J.; Yang, C.-C.; Hsu, M.-Y.; Kan, L.-C.; Lee, C.-L.; Yu, T.-C.; Peng, R.-D.; Yang, C.-L.; Hwang, Y.-S.; Lee, J.-K.; Tsao, S.-L.; CHIA-LIN YANG ; MING OUHYOUNG | ISPASS 2017 - IEEE International Symposium on Performance Analysis of Systems and Software | 3 | 0 | |
2021 | Analyzing the Interplay between Random Shuffling and Storage Devices for Efficient Machine Learning | Ke Z.-L; Cheng H.-Y; Yang C.-L; Huang H.-W.; CHIA-LIN YANG | Proceedings - 2021 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2021 | | | |
1999 | Annotated memory references: A mechanism for informed cache management | CHIA-LIN YANG ; Lebeck, A.R.; Raymond, D.R.; Yang, C.-L.; Thottethodi, M.S.; CHIA-LIN YANG | Lecture Notes in Computer Science | | | |
1999 | Annotated Memory References: A Mechanism for Informed Cache Management. | Lebeck, Alvin R.; Raymond, David R.; CHIA-LIN YANG ; Thottethodi, Mithuna | Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31 - September 3, 1999, Proceedings | 2 | 0 | |
2009 | An architectural co-synthesis algorithm for energy-aware network-on-chip design. | Hung, Wei-Hsuan; Chen, Yi-Jung; Chang, Yen-Sheng; CHIA-LIN YANG | Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), Seoul, Korea, March 11-15, 2007 | 4 | 0 | |
2021 | Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization | Wei M.-L; Yayla M; Ho S.-Y; Chen J.-J; Yang C.-L; Amrouch H.; CHIA-LIN YANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | | | |
2007 | Bioroute: A Network-Flow Based Routing Algorithm for Digital Microfluidic Biochips | Yuh, Ping-Hung; Yang, Chia-Lin ; CHIA-LIN YANG | IEEE/ACM International Conference on Computer-Aided Design | 82 | 0 | |
2008 | BioRoute: A network-flow-based routing algorithm for the synthesis of digital microfluidic biochips | Yuh, Ping-Hung; YAO-WEN CHANG ; CHIA-LIN YANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 77 | 55 | |
2006 | Branch Behavior Characterization for Multimedia Applications | Yang, Chia Lin ; Wang, Shun Ying; Chen, Yi Jung | Lecture Notes in Computer Science | | | |
2006 | Branch behavior characterization for multimedia applications | CHIA-LIN YANG ; Yang, C.-L.; Wang, S.-Y.; Chen, Y.-J.; CHIA-LIN YANG | Lecture Notes in Computer Science | | | |
2006 | Branch behavior characterization for multimedia applications | Yang, Chia-Lin; Wang, Shun-Ying; Chen, Yi-Jung; CHIA-LIN YANG | Advances in Computer Systems Architecture, Proceedings | | | |
2006 | Branch Behavior Characterization for Multimedia Applications. | Yang, Chia-Lin; Wang, Shun-Ying; Chen, Yi-Jung; CHIA-LIN YANG | Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings | | | |
2015 | A buffer cache architecture for smartphones with hybrid DRAM/PCM memory. | Lin, Ye-Jyun; Yang, Chia-Lin; Li, Hsiang-Pang; CHIA-LIN YANG | IEEE Non-Volatile Memory System and Applications Symposium, NVMSA 2015, Hong Kong, China, August 19-21, 2015 | 14 | 0 | |