公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2006 | An Energy-Efficient Virtual Memory System with Flash Memory as the Secondary Storage | Tseng, Hung-Wei; Li, Han-Lin; Yang, Chia-Lin | 2006 International Symposium on Low Power Electronics and Design | | | |
2006 | An energy-efficient virtual memory system with flash memory as the secondary storage. | Tseng, Hung-Wei; Li, Han-Lin; CHIA-LIN YANG | Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006 | | | |
1998 | Exploiting instruction level parallelism in geometry processing for three dimensional graphics applications | CHIA-LIN YANG ; Yang, Chia-Lin; Sano, Barton; Lebeck, Alvin R.; CHIA-LIN YANG | Annual International Symposium on Microarchitecture | | | |
1998 | Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. | Yang, Chia-Lin; Sano, Barton; Lebeck, Alvin R.; CHIA-LIN YANG | Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 31, Dallas, Texas, USA, November 30 - December 2, 1998 | | | |
2000 | Exploiting parallelism in geometry processing with general purpose processors and floating-point SIMD instructions | CHIA-LIN YANG ; Yang, C.-L.; Sano, B.; Lebeck, A.R.; CHIA-LIN YANG | IEEE Transactions on Computers | | | |
2017 | Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives | Chang, C.-W.; Chen, G.-Y.; Chen, Y.-J.; Yeh, C.-W.; Eng, P.Y.; Cheung, A.; Yang, C.-L.; CHIA-LIN YANG | IEEE Transactions on Computers | | | |
2013 | Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. | Lin, Ping-Sheng; Chen, Yi-Jung; Yang, Chia-Lin; YI-CHANG LU ; CHIA-LIN YANG | International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, 2013 | 2 | 0 | |
2019 | Fair Down to the Device: A GC-Aware Fair Scheduler for SSD. | Ji, Cheng; Wang, Lun; Li, Qiao; Gao, Congming; Shi, Liang; Yang, Chia-Lin; Xue, Chun Jason; CHIA-LIN YANG | 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2019, Hangzhou, China, August 18-21, 2019 | | | |
2015 | Fine-grained write scheduling for PCM performance improvement under write power budget. | Lai, Chun-Hao; Yu, Shun-Chih; Yang, Chia-Lin; CHIA-LIN YANG | IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015, Rome, Italy, July 22-24, 2015 | 6 | 0 | |
2020 | FlashEmbedding: Storing embedding tables in SSD for large-scale recommender systems | Wan H; Sun X; Cui Y; CHIA-LIN YANG ; TEI-WEI KUO ; Xue C.J. | APSys 2021 - Proceedings of the 12th ACM SIGOPS Asia-Pacific Workshop on Systems | 9 | 0 | |
2022 | A Forward Speculative Interference Attack | CHIA-LIN YANG ; Vetter, Ron | Computer | 0 | 0 | |
2014 | Full system simulation framework for integrated CPU/GPU architecture | Wang, P.-H.; Liu, G.-H.; Yeh, J.-C.; Chen, T.-M.; Huang, H.-Y.; Yang, C.-L.; Liu, S.-L.; CHIA-LIN YANG | Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test | 6 | 0 | |
2021 | Future Computing Platform Design: A Cross-Layer Design Approach | Cheng H.-Y; Wu C.-F; Hakert C; Chen K.-H; Chang Y.-H; Chen J.-J; Yang C.-L; CHIA-LIN YANG ; TEI-WEI KUO | Proceedings -Design, Automation and Test in Europe, DATE | 6 | 0 | |
2012 | Guest editorial: Special issue for the 23 rd VLSI design/CAD symposium (VLSI design/CAD 2012) | Lee, T.-C.; Chien, S.-Y.; CHIA-LIN YANG | International Journal of Electrical Engineering | | | |
2012 | Guest editorial: Special issue for the 23rd VLSI design/CAD symposium (VLSI design/CAD 2012) | CHIA-LIN YANG ; Lee, T.-C.; Chien, S.-Y.; Yang, C.-L.; CHIA-LIN YANG | International Journal of Electrical Engineering | | | |
2014 | Guest editors' introduction: Cloud computing for embedded systems | Dimitrov, M.; Lu, Y.-H.; CHIA-LIN YANG | IEEE Design and Test | 2 | 2 | |
2010 | Hierarchical memory scheduling for multimedia MPSoCs | Lin, Y.-J.; Yang, C.-L.; Lin, T.-J.; Huang, J.-W.; CHIA-LIN YANG | IEEE/ACM International Conference on Computer-Aided Design | 9 | 0 | |
2006 | Hierarchical Value Cache Encoding for Off-Chip Data Bus | Lin, Chung-Hsiang; Yang, Chia-Lin ; King, Ku-Jei | 2006 International Symposium on Low Power Electronics and Design | | | |
2006 | Hierarchical value cache encoding for off-chip data bus. | Lin, Chung-Hsiang; Yang, Chia-Lin; King, Ku-Jei; CHIA-LIN YANG | Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006 | | | |
2004 | HotSpot cache: joint temporal and spatial locality exploitation for I-cache energy reduction | Yang, Chia-Lin ; Lee, Chien-Hao | 2004 International Symposium on Low Power Electronics and Design | 0 | 0 | |