公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2008 | Obstacle-avoiding rectilinear steiner tree construction based on spanning graphs | Chen, S.-Y.; Li, C.-F.; CHIA-LIN YANG ; CHUNG-WEI LIN ; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 53 | 46 | |
2016 | Opportunities of Synergistically Adjusting Voltage-Frequency Levels of Cores and DRAMs in CMPs with 3D-Stacked DRAMs for Efficient Thermal Control | Chen, Yi-Jung; Yang, Chia-Lin; Lin, Pin-Sheng; Lu, Yi-Chang; CHIA-LIN YANG | Applied Computing Review | 5 | 0 | |
2012 | Optimizing NAND flash-based SSDs via retention relaxation. | Liu, Ren-Shuo; CHIA-LIN YANG ; Wu, Wei | Proceedings of the 10th USENIX conference on File and Storage Technologies, FAST 2012, San Jose, CA, USA, February 14-17, 2012 | 105 | | |
2010 | Parallelization and characterization of GARCH option pricing on GPUs. | Liu, Ren-Shuo; Tsai, Yun-Cheng; CHIA-LIN YANG | Proceedings of the 2010 IEEE International Symposium on Workload Characterization, IISWC 2010, Atlanta, GA, USA, December 2-4, 2010 | 3 | 0 | |
2005 | Phase-Aware I-Cache Size Synthesis with QoS Consideration | Chen, Yi-Jung; Yang, Chia-Lin ; Lin, En-Kai | Asia and South Pacific International Conference on Embedded SoCs | | | |
2006 | Placement of digital microfluidic biochips using the T-tree formuation | Yuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen | 43rd annual Design Automation Conference | | | |
2006 | Placement of digital microfluidic biochips using the t-tree formulation | Yuh, P.-H.; Yang, C.-L.; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings - Design Automation Conference | 44 | 0 | |
2010 | PM-COSYN: PE and memory co-synthesis for MPSoCs | Chen, Y.-J.; Yang, C.-L.; Wang, P.-H.; CHIA-LIN YANG | Design, Automation and Test in Europe | | | |
2010 | PM-COSYN: PE and memory co-synthesis for MPSoCs. | Chen, Yi-Jung; Yang, Chia-Lin; Wang, Po-Han; CHIA-LIN YANG | Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010 | 0 | 0 | |
2007 | Post Placement Leakage Optimization for Partially Dynamic Reconfigurable FPGAs | Li, Chi-Feng; Yuh, Ping-Hung; Yang, Chia-Lin ; CHIA-LIN YANG | International Symposium on Low Power Electronics and Design | 7 | 0 | |
2011 | Power gating strategies on GPUs | Wang, P.-H.; Yang, C.-L.; Chen, Y.-M.; Cheng, Y.-J.; CHIA-LIN YANG | Transactions on Architecture and Code Optimization | 41 | 37 | |
2003 | A power-aware SWDR cell for reducing cache write power. | Chang, Yen-Jen; Yang, Chia-Lin; Lai, Feipei; CHIA-LIN YANG | Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003 | 0 | 0 | |
2009 | PPT: Joint performance/power/thermal management of DRAM memory for multi-core systems | Lin, C.-H.; Yang, C.-L.; CHIA-LIN YANG | International Symposium on Low Power Electronics and Design | 22 | 0 | |
2004 | Profit-Driven Uniprocessor Scheduling with Energy and Timing Constraints | Chen, Jian-Jia; Kuo, Tei-Wei ; Yang, Chia-Lin | 2004 ACM symposium on Applied computing | | | |
2004 | Profit-driven uniprocessor scheduling with energy and timing constraints. | Chen, Jian-Jia; Kuo, Tei-Wei; CHIA-LIN YANG ; TEI-WEI KUO | Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), Nicosia, Cyprus, March 14-17, 2004 | 17 | 0 | |
2002 | A programmable memory hierarchy for prefetching linked data structures | Yang, C.-L.; Lebeck, A.; CHIA-LIN YANG | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | 3 | 0 | |
2002 | A Programmable Memory Hierarchy for Prefetching Linked Data Structures. | Yang, Chia-Lin; Lebeck, Alvin R.; CHIA-LIN YANG | High Performance Computing, 4th International Symposium, ISHPC 2002, Kansai Science City, Japan, May 15-17, 2002, Proceedings | 3 | 0 | |
2008 | A progressive-ILP based routing algorithm for cross-referencing biochips. | Yuh, Ping-Hung; Sapatnekar, Sachin S.; Yang, Chia-Lin; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008 | 0 | 0 | |
2022 | PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support | Lin C.-H; Lin S.-F; Chen Y.-J; Jenp E.-Y; CHIA-LIN YANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 0 | 0 | |
2000 | Push vs. pull: Data movement for linked data structures | Yang, Chia-Lin; Lebeck, Alvin R.; CHIA-LIN YANG | International Conference on Supercomputing | | | |