公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2008 | Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise, | Hsiu-Ting Lin; Jen-Yang Wen; James Li; Ming-Tung Chang; Min-Hsiu Tsai; Sheng-Chih Huang; Chih-Mou Tseng; CHIEN-MO LI | Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise | 1 | 0 | |
2021 | Chip Performance Prediction Using Machine Learning Techniques | Su M.-Y; Lin W.-C; Kuo Y.-T; Li C.-M; Fang E.J.-W; Hsueh S.S.-Y.; CHIEN-MO LI | 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings | 5 | 0 | |
2021 | Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits | Chen T.-C; Pai C.-C; Hsieh Y.-Z; Tseng H.-Y; Chien-Mo J; Liu T.-T; CHIEN-MO LI ; TSUNG-TE LIU ; Chiu I.-W | Journal of Electronic Testing: Theory and Applications (JETTA) | 0 | 0 | |
2005 | Column Parity and Row Select (CPRS): BIST Diagnosis for Errors in Multiple Scan Chains | H.M. Lin; J. C. M. Li; CHIEN-MO LI | International Test Conference | 11 | 0 | |
2007 | Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis | J. C.-M. Li; Hung-Mao Lin; Fang Min Wang; CHIEN-MO LI | IEEE Transactions on Computers | 7 | 3 | |
2013 | Compact Test Pattern Selection for Small Delay Defect | J. Y. Chang; K. Y. Liao; S. C. Hsu; J. C. M. Li; J. C. Rau; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 17 | 18 | |
2011 | Compact test pattern Selection for Small Delay Defects | CY Chang; K.Y, Liao; J.CM Li; CHIEN-MO LI | VLSI/CAD | | | |
2006 | CRC BIST: A Low Peak Power Self Technique | Bo-Hua Chen; J. C.-M. Li; CHIEN-MO LI | VLSI/CAD | | | |
2010 | CSER: BISER-based concurrent soft-error resilience | Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI ; JIUN-LANG HUANG | VLSI Test Symposium (VTS) | 2 | 0 | |
2007 | Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies | C.Y. Lee; H.M. Lin; F.M. Wang; J. C. M. Li; CHIEN-MO LI | IEEE Asian South Pacific Design Automation Conference (ASP-DAC) | 0 | 0 | |
2013 | Defect Analysis and Fault Modeling for Rnv8T Nonvolatile SRAM | Bing-Chuan Bai; Chen-An Chen; Yee-Wen Chen; Ming-Hsueh Wu; Kun-Lun Luo; Chun-Lung Hsu; Liang-Chia Cheng; Chien-Mo Li; CHIEN-MO LI | IEEE Int’l Test Conf. | | | |
2007 | Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing | Chun-Yi Lee; James C.-M. Li; CHIEN-MO LI | Journal of Low Power Electronic | 0 | 0 | |
2004 | Design and Implementation of a Low Power Delay Fault Built-in Self Test Technique | L. W. Ko; C.M. Li; CHIEN-MO LI | VLSI/CAD Symposium | | | |
2014 | Detect RRAM Defects in The Early Stage During Rnv8T Nonvolatile SRAM Testing | B.C. Bai; C.A. Chen; J C.M Li; CHIEN-MO LI | IEEE International Test Conference | | | |
2010 | DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in | W.-C. Kao; W.-S. Chuang; H.-T. Lin; J. C.-M. Li; V, Manquinho; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 3 | 1 | |
2022 | Diagnosing Double Faulty Chains through Failing Bit Separation | Kuo, Cheng Sian; Hsieh, Bing Han; CHIEN-MO LI ; Nigh, Chris; Bhargava, Gaurav; Chern, Mason | Proceedings - International Test Conference | 0 | 0 | |
2018 | Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations | Li, Y.-C.; Lin, S.-Y.; Lin, H.-Y.; Li, J.C.-M.; CHIEN-MO LI | 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 | 1 | 0 | |
2002 | Diagnosis for Sequence Dependent Chips | Li, J. C.M.; E. J. McCluskey; CHIEN-MO LI | IEEE VLSI Test Symposium | 44 | 0 | |
2008 | Diagnosis of Logic-chain Bridging Faults | Wei-Chih Liu; Wei-Lin Tsai; Hsiu-Ting Lin; James Chien-Mo Li; CHIEN-MO LI | IEEE Int’l Workshop on RTL and High Level Testing | 0 | 0 | |
2005 | Diagnosis of Multiple Hold-time and Setup-time Faults in Scan Chains | CHIEN-MO LI | IEEE Transactions on Computers | | 31 | |