公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2008 | On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs | Wu, S.; Wang, L.-T.; Jiang, Z.; Song, J.; Sheu, B.; Wen, X.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; CHIEN-MO LI ; JIUN-LANG HUANG | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | 1 | 0 | |
2018 | Parallel order ATPG for test compaction | Chen, Y.-W.; Ho, Y.-H.; Chang, C.-M.; Yang, K.-C.; Li, M.-T.; Li, J.C.-M.; CHIEN-MO LI | 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 | 5 | 0 | |
2008 | Phase Noise Testing of Single Chip TV Tuners, | P.-C. Lin; C.-H. Hsu; J. C.-M. Li; C.-M. Chiang; C.-J. Pan,; CHIEN-MO LI | IEEE VLSI-DAT | 0 | 0 | |
2017 | Physical-aware diagnosis of multiple interconnect defects | Chen, P.-H.; Lee, C.-L.; Chen, J.-Y.; Chen, P.-W.; CHIEN-MO LI | ITC-Asia 2017 - International Test Conference in Asia | 2 | 0 | |
2014 | Physical-aware Systematic Multiple Defect Diagnosis | P. J. Chen; C. C. Che; J. C. M. Li; S. F. Kuo; P. Y. Hsueh; C. Y. Kuo; J. N. Lee; CHIEN-MO LI | IET Proceedings Computers and Digital Techniques | 12 | 10 | |
2011 | Placement optimization of flexible TFT digital circuits | Liu, W.-H.; Ma, E.-H.; Wei, W.-E.; Li, J.C.-M.; CHIEN-MO LI | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 1 | 0 | |
2011 | Placement optimization of flexible TFT digital circuits | Liu, C.; Ma, E.-H.; Wei, W.-E.; Li, J.; Cheng, I.-C.; Yeh, Y.-H.; I-CHUN CHENG ; CHIEN-MO LI | IEEE Design and Test of Computers | 4 | 4 | |
2009 | Power Scan: DFT for Power Switches in VLSI Designs | CHIEN-MO LI | International Test Conference | | | |
2009 | Power scan: OFT for power switches in VLSI designs | Bai, B.-C.; Li, C.-M.; Kifli, A.; Tsai, E.; CHIEN-MO LI | Proceedings - International Test Conference | 0 | 0 | |
2014 | Power-Supply-Noise-Aware Dynamic Timing Analyzer for 3D IC | H.Y. Hsieh; J. C.-M. Li; CHIEN-MO LI | IEEE 3D IC Test Workshop | | | |
2016 | Power-supply-noise-aware timing analysis and test pattern regeneration | Han, C.-Y.; Li, Y.-C.; Kan, H.-T.; Li, J.C.-M.; CHIEN-MO LI | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 0 | 0 | |
2001 | Pseudo Random Testing Theoretical Models vs. Real Data | Mitra; S.; C.W. Tseng; J. C. M Li; E. J. McCluskey; CHIEN-MO LI | IEEE International Workshop on Test Resource Partitioning | | | |
2017 | PSN-aware Circuit Test Timing Prediction using Machine Learning | B. Liu; J. C.M. Li; CHIEN-MO LI | IET Computers & Digital Techniques | 9 | 6 | |
2011 | Reliability and Validity Evidence of the Chinese Piers-Harris Children's Self-Concept Scale Scores Among Taiwanese Children | Flahive, Mon-hsin Wang; Chuang, Ying-Chih; Li, Chien-Mo; CHIEN-MO LI | Journal of Psychoeducational Assessment | 9 | 7 | |
2010 | Reliability screening of a-Si TFT circuits: Very-low voltage and I <inf>DDQ</inf> Testing | Shen, S.-T.; Liu, C.; Ma, E.-H.; Cheng, I.-C.; Li, J.C.-M.; I-CHUN CHENG ; CHIEN-MO LI | IEEE/OSA Journal of Display Technology | 2 | 1 | |
2007 | Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique | B.-H. Chen; Wei-Chuang Kao; Bin-Chuan Bai; Shyue-Tsong Shen; James C.-M. Li; CHIEN-MO LI | IEEE Asian Test Symposium | 0 | 0 | |
2017 | Robust test pattern generation for hold-time faults in nanometer technologies | Ho, Y.-H.; Chen, Y.-W.; Chang, C.-M.; Yang, K.-C.; Li, J.C.-M.; CHIEN-MO LI | 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 | 1 | 0 | |
2010 | Row-LFSR-Column (RLC) Test Response Masking Technique | WC Wang; JCM Li; CHIEN-MO LI | VLSI/CAD | | | |
2011 | Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips | W.C. Wang; J.C.M Li; CHIEN-MO LI | IET Computers & Digital Techniques | 2 | 2 | |
2005 | Segmented Weighted Random BIST (SWR-BIST) Technique for Low Power Testing | Lee, C-Y; Li, C-M; CHIEN-MO LI | Asia Solid-State Circuit Conference (ASSCC) | 1 | 0 | |