公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2015 | A low-power low-latency processor for real-time on-line local mean decomposition | Hsueh, H.-C.; Chien, S.-Y.; SHAO-YI CHIEN | 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 | 1 | 0 | |
2010 | A multimedia semantic analysis SoC (SASoC) with machine-learning engine | Chen, T.-W.; Chen, Y.-L.; Cheng, T.-Y.; Tang, C.-S.; Tsung, P.-K.; Chuang, T.-D.; LIANG-GEE CHEN ; SHAO-YI CHIEN | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 14 | 0 | |
2010 | A no -reference quality evaluation method for CFA demosaicking | Liu, Y.-N.; Lin, Y.-C.; Chien, S.-Y.; SHAO-YI CHIEN | ICCE 2010 - 2010 International Conference on Consumer Electronics | 9 | 0 | |
2001 | A partial-result-reuse architecture and its design technique for morphological operations | Chien, S.-Y.; Ma, S.-Y.; Chen, L.-G.; SHAO-YI CHIEN | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | | | |
2001 | A real-time practical video segmentation algirithm for MPEG-4 camera systems | Chien, Shao-Yi ; Huang, Yu-Wen; Ma, Shyh-Yih; Chen, Liang-Gee | IEEE International Conference on Consumer Electronics | 0 | 0 | |
2015 | A virtual touching scheme for interactive TV using a consumer depth camera | Fan, S.-P.; Huang, Y.-L.; Chien, S.-Y.; SHAO-YI CHIEN | 2015 IEEE International Conference on Consumer Electronics, ICCE 2015 | 0 | 0 | |
2019 | Accelerator Design for Vector Quantized Convolutional Neural Network | Wu, Y.-H.; Lee, H.; Lin, Y.S.; Chien, S.-Y.; SHAO-YI CHIEN | Proceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019 | 2 | 0 | |
2006 | Adaptive tile depth filter for the depth buffer bandwidth minimization in the low power graphics systems | Tsao, Y.-M.; Wu, C.-L.; Chien, S.-Y.; Chen, L.-G.; SHAO-YI CHIEN | IEEE International Symposium on Circuits and Systems | | | |
2006 | Adaptive tile depth filter for the depth buffer bandwidth minimization in the low power graphics systems. | Tsao, You-Ming; Wu, Chi-Ling; Chien, Shao-Yi; LIANG-GEE CHEN ; SHAO-YI CHIEN | International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece | 0 | 0 | |
2013 | Algorithm adaptive video deinterlacing using self-validation framework | Wang, T.-C.; Liu, Y.-N.; Chien, S.-Y.; SHAO-YI CHIEN | IEEE International Symposium on Circuits and Systems | 1 | 0 | |
2014 | Algorithm and architecture design of high-quality video upscaling using database-free texture synthesis | Liu, Y.-N.; Lin, Y.-C.; Huang, Y.-L.; Chien, S.-Y.; SHAO-YI CHIEN | IEEE Transactions on Circuits and Systems for Video Technology | 7 | 5 | |
2011 | Algorithm and architecture design of image inpainting engine for video error concealment applications | Wu, G.-L.; Chen, C.-Y.; Chien, S.-Y.; SHAO-YI CHIEN ; Chen, Ching-Yi | IEEE Transactions on Circuits and Systems for Video Technology | 15 | 13 | |
2009 | Algorithm and architecture design of multi-layer video coding engine with hybrid scheme for wireless video links | Huang, K.-H.; Chen, H.-R.; Chien, S.-Y.; SHAO-YI CHIEN | 2009 IEEE International Conference on Multimedia and Expo, ICME 2009 | 0 | 0 | |
2017 | Algorithm and Architecture Design of Multirate Frame Rate Up-conversion for Ultra-HD LCD Systems | Huang, Y.-L.; Chen, F.-C.; Chien, S.-Y.; SHAO-YI CHIEN | IEEE Transactions on Circuits and Systems for Video Technology | 11 | 10 | |
2011 | Algorithm and architecture design of perception engine for video coding applications | Wu, G.-L.; Wu, T.-H.; Chien, S.-Y.; SHAO-YI CHIEN | IEEE Transactions on Multimedia | 10 | 6 | |
2005 | Algorithm and architecture of prediction core in stereo video hybrid coding system | Ding, L.-F.; SHAO-YI CHIEN ; LIANG-GEE CHEN | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 2 | 0 | |
2002 | Algorithm and architecture of video segmentation hardware system with a programmable PE array | Chien, Shao-Yi ; Huang, Yu-Wen; Hsieh, Bing-Yu; LIANG-GEE CHEN | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 1 | 0 | |
2006 | Algorithm and hardware architecture design for weighted prediction in H.264/MPEG-4 AVC. | Tang, Chi-Sun; Tsai, Chen-Han; Chien, Shao-Yi; LIANG-GEE CHEN ; SHAO-YI CHIEN | International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece | 0 | 0 | |
2007 | An 8.6mW 12.5Mvertices/s 800MOPS 8.91mm2 stream processor core for mobile graphics and video applications | Tsao, Y.-M.; Chang, C.-H.; Lin, Y.-C.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN ; Chien, Shao-Yi | IEEE Symposium on VLSI Circuits | 9 | 0 | |
2008 | An 8.6mW 25Mvertices/s 400-MFLOPS 800-MOPS 8.91mm2 multimedia stream processor core for mobile applications | Chien, Shao-Yi ; Tsao, You-Ming; Chang, Chin-Hsiang; Lin, Yu-Cheng | IEEE Journal of Solid-State Circuits | 11 | 7 | |