公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2017 | PSN-aware Circuit Test Timing Prediction using Machine Learning | B. Liu; J. C.M. Li; CHIEN-MO LI | IET Computers & Digital Techniques | 9 | 6 | |
2011 | SI-aware layout and equalizer design to enhance performance of high-speed links in blade servers | Y.-S. Cheng; H.-H. Lu; M. Chang; S. Chang; B. Liu; RUEY-BEEI WU | IEEE 20th Topical Meeting on Electrical Performance of Electronic Packaging | |||
2013 | SI-aware vias and contact pads layouts and L-R equalization technique for 12Gb/s backplane serial I/O interconnections | Y.-S. Cheng; B. Liu; RUEY-BEEI WU | IEEE Transactions on Electromagnetic Compatibility | 3 |