公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2004 | Efficient power/ground network analysis for power integrity-driven design methodology. | Wu, Su-Wei; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004 | 21 | 0 | |
2012 | An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs | Lin, Chung-Wei; Lee, Po-Wei; Chang, Yao-Wen; Shen, Chin-Fang; YAO-WEN CHANG ; CHUNG-WEI LIN | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 16 | 14 | |
2009 | An efficient pre-assignment routing algorithm for flip-chip designs. | Lee, Po-Wei; Lin, Chung-Wei; Chang, Yao-Wen; Shen, Chin-Fang; CHUNG-WEI LIN ; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 15 | 0 | |
1996 | Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation | Chen, Chung-Ping; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG | Design Automation Conference | 24 | | |
1996 | Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. | Chen, Chung-Ping; Chang, Yao-Wen; Wong, D. F.; YAO-WEN CHANG | Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996. | 24 | 0 | |
2006 | Floorplan and power/ground network co-synthesis for fast design convergence. | Liu, Chen-Wei; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006 | 22 | 0 | |
2002 | Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. | Chang, Nicholas Chia-Yuan; Chang, Yao-Wen; YAO-WEN CHANG ; HUI-RU JIANG | 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002 | 1 | 0 | |
2007 | Full-Chip Nanometer Routing Techniques. | Ho, Tsung-Yi; Chang, Yao-Wen; Chen, Sao-Jie; YAO-WEN CHANG | | | | |
1999 | Generic universal switch blocks | Shyu, Michael; Chang, Yu-Dong; Wu, Guang-Ming; Chang, Yao-Wen; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 1 | 0 | |
2003 | Graph matching-based algorithms for array-based FPGA segmentation design and routing. | Lin, Jai-Ming; Pan, Song-Ra; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003 | 0 | 0 | |
2006 | A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. | Chen, Tung-Chieh; Jiang, Zhe-Wei; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
2015 | Identification of a novel platelet antagonist that binds to CLEC-2 and suppresses podoplanin-induced platelet aggregation and cancer metastasis | Chang, Yao-Wen; Hsieh, Pei-Wen; Chang, Yu-Tsui; Lu, Meng-Hong; TUR-FU HUANG ; Chong, Kowit-Yu; Liao, Hsiang-Ruei; Cheng, Ju-Chien; YAO-WEN CHANG | Oncotarget | 74 | 62 | |
2007 | An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. | Lee, Wan-Ping; Liu, Hung-Yi; Chang, Yao-Wen; YAO-WEN CHANG | 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007 | 57 | 0 | |
2007 | An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. | Fang, Jia-Wei; Hsu, Chin-Hsiung; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007 | 0 | 0 | |
2004 | Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. | Cheng, Yi-Hui; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |
2017 | An Interview With Professor Chenming Hu, Father of 3D Transistors | Chang, Yao-Wen; Hu, Chenming; YAO-WEN CHANG | Ieee Design & Test | 0 | 0 | |
2004 | Layout techniques for on-chip interconnect inductance reduction. | Tu, Shang-Wei; Jou, Jing-Yang; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |
1998 | Maximally routable switch matrices for FPD design | Wu, Guang-Min; Chang, Yao-Wen; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 0 | | |
2005 | Modern floorplanning based on fast simulated annealing. | Chen, Tung-Chieh; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005 | 59 | 0 | |
2007 | MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. | Chen, Tung-Chieh; Yuh, Ping-Hung; Chang, Yao-Wen; Huang, Fwu-Juh; Liu, Denny; YAO-WEN CHANG | Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007 | 0 | 0 | |