公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2005 | EPEEC: Comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates | Jiang, R.; Fu, W.; CHUNG-PING CHEN | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |