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J. B. Kuo
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作者
來源出版物
scopus
WOS
全文
2014
Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC
G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
Asia Pacific CSEE Conference
1999
Low-Voltage CMOS VLSI Circuits
J. B. Kuo; J. H. Lou; JAMES-B KUO
2001
Low-Voltage Content Addressable Memory Cell with a Fast Tag-Compare Capability Using Partially-Depleted SOI CMOS Dynamic-Threshold Techniques
J. B. Kuo; S. C. Liu; JAMES-B KUO
2007
Low-Voltage Single-Phase Clocking Adiabatic DCVS Logic Circuit with Pass Gate Logic
E. K. Loo; J. B. Kuo; M. Syrzycki; JAMES-B KUO
Canadian Conference on Electrical and Computer Engineering
2010
Low-Voltage SOI CMOS DTMOS/MTCMOS Circuit Technique for Design Optimization of Low-power SOC Applications
W.C.H. Lin; J. B. Kuo; JAMES-B KUO
ISCAS
0
0
2001
Low-Voltage SOI CMOS VLSI Devices and Circuits
J. B. Kuo; S. C. Lin; JAMES-B KUO
2004
Low-Voltage SOI CMOS VLSI Devices and Circuits
J. B. Kuo; S. C. Lin; JAMES-B KUO
2012
Modeling Hot-Carrier-Induced Reliability of Poly-silicon Thin Film Transistors
L. L. Wang; J. B. Kuo; S. Zhang; JAMES-B KUO
IEEE International Conference on Electron Devices and Solid State Circuit
0
0
2001
Modeling of Single-Transistor Latch Behavior in Partially-Depleted (PD) SOI CMOS Devices Using a Concise SOI-SPICE Model
J. B. Kuo; S. C. Lin; JAMES-B KUO
International Conference on Semiconductor IC Technology (ICSICT)
1
0
2007
Modeling the Drain Current of DG FD SOI NMOS Devices with N+/P+ Top/Bottom Gate
C. H. Hsu; J. B. Kuo; JAMES-B KUO
Electron Devices and Solid State State Circuits (EDSSC) Conf
0
0
2010
Modeling the Floating-Body-Effect-Induced Drain Current Behavior of 40nm PD SOI NMOS Device Via SPICE BJT/MOS Model Approach
J. S. Su; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
EUROSOI
2009
Modeling the Floating-Body-Effect-Induced Drain Current Behavior of PD SOI NMOS Device Via SPICE BJT/MOS Model Approach
J. S. Su; J. B. Kuo; JAMES-B KUO
Compact TFT Modeling Workshop
0
0
2011
Modeling the Floating-Body-Effect-Related Transient Behavior of 40nm PD SOI NMOS Device via the SPICE Bipolar/MOS Model
S. W. Fang; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
International Semiconductor Device Research Symposium ISDRS
1
0
2003
Modeling the Fringing Electric Field Effect on the Threshold Voltage of FD SOI NMOS Devices with the LDD/Sidewall Oxide Spacer Structure
S. C. Lin; J. B. Kuo; JAMES-B KUO
IEEE Transactions on Electron Devices
74
64
2014
MTCMOS Low-Power Design Technique (LPDT) for Low-Voltage Piepelined Mcoprocessor Circuit
C. B. Hsu; J. B. Kuo; JAMES-B KUO
ISIC
1
0
2014
MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit
C. B. Hsu; Y. S. Hong; J. B. Kuo; JAMES-B KUO
ICECS
1
0
2007
Narrow Band Gap Semiconductor
H. H. Lin; J. B. Kuo; JAMES-B KUO
Wiley's Electrical Engineering Encyclopedia
2001
Novel 0.8V True-Single-Phase-Clocking (TSPC) Latches Using PD-SOI DTMOS Techniques for Low-Voltage CMOS VLSI Circuits
J. B. Kuo; T. Y. Chiang; JAMES-B KUO
IEEE SOI Conference Proceedings
0
0
2013
Novel Power Consumption Reduction strategy Using Mixed-Vth Cells for Optimizaing the Cells on Critical Paths for Low-Power SOC
G. Lin; J. B. Kuo; JAMES-B KUO
International Conference on EECS
2003
Novel Sub-1V CMOS Domino Dynamic Logic Circuit Using a Direct Bootstrap (DB) Technique for Low-voltage CMOS VLSI
P. C. Chen; J. B. Kuo; JAMES-B KUO
International Symposium on Circuits and Systems
0
0