公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2007 | An Efficient Peak Power Reduction Technique for Scan Testing | M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 18 | 0 | |
2010 | An Error Tolerance Scheme for 3D CMOS Imagers | H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG | Design Automation Conference | 13 | 0 | |
2013 | An IDDQ-Based Source Driver IC Design-for-Test Technique | S.-S. Lin; C.-L. Kao; J.-L. Huang; C.-C. Lee; X.-L. Huang; JIUN-LANG HUANG | International Conference on Computer-Aided Design | 0 | 0 | |
2010 | An Improved Weight Assignment Scheme for IR-Drop-Aware At-Speed Scan Pattern Generation | M.-F. Wu; H.-C. Pan; T.-H. Wang; J.-L. Huang; K.-H. Tsai; W.-T. Cheng; JIUN-LANG HUANG | Asia and South Pacific Design Automation Conference | |||
2012 | An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration | X.-L. Huang; J.-L. Huang; H.-I. Chen; C.-Y. Chen; K.-T. Tseng; M.-F. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 5 | 5 | |
2009 | An On-Chip Integrator Leakage Characterization Technique and Its Applications to Switched Capacitor Circuits Testing | C.-Y. Yang; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 1 | 0 | |
2006 | An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testing | S.-W. Chang; J.-L. Huang; JIUN-LANG HUANG | VLSI Design/CAD Symposium | |||
2010 | A robust ADC code hit counting technique | J.-L. Huang; Kuo-Yu Chou; Ming-Huan Lu; Xuan-Lun Huang; JIUN-LANG HUANG | Design, Automation & Test in Europe | 1 | ||
2011 | Broadcast test pattern generation considering skew-insertion and partial-serial scan | C.-J. Lin; J.-L. Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 3 | 0 | |
2008 | Calibrating Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signals, Sensors, and Systems Test Workshop | 6 | 0 | |
2009 | Ch. 8 Logic and Circuit Simulation | J.-L. Huang; C.-K. Koh; S. F. Cauley; JIUN-LANG HUANG | Electronic Design Automation: Synthesis, Verification, and Test | |||
2007 | Chap. 11 Software-Based Self-Testing | J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | System on Chip Test Architectures | |||
2006 | Chap. 3: Logic and Fault Simulation | J.-L. Huang; James C.-M. Li; Duncan M. (Hank) Walker; JIUN-LANG HUANG | VLSI Test Principles and Architectures | |||
2009 | Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC Input | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | Asia and South Pacific Design Automatic Conference | |||
2011 | Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing | Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG | International Test Conference | 3 | 0 | |
2016 | CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator | K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 1 | 1 | |
2017 | Design and implementation of an EG-pool based FPGA formatter with temperature compensation | Y.-K. Huang; K.-T. Li; C.-L. Hsiao; C.-A. Lee; J.-L. Huang; T. Kuo; JIUN-LANG HUANG | Asian Test Symposium | 2 | 0 | |
2015 | Design and Implementation of an FPGA-Based Data/Timing Formatter | Y.-Y. Chen; J.-L. Huang; T. Kuo; X.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 6 | 6 | |
2008 | Design of a Fault Tolerant Carry Lookahead Adder | C.-Y. Huang, T.-H. Ko; J.-L. Huang; JIUN-LANG HUANG | International Test Synthesis Workshop | |||
2006 | Extracting Random Jitter in the Existence of Sinusoidal Jitter | J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signal Testing Workshop |