公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2014 | A silicon nanowire-based bio-sensing system with digitized outputs for acute myocardial infraction diagnosis | Shen, S.-H.; Ting, C.-Y.; Liu, C.-Y.; Cheng, H.; Liu, S.-I.; CHIH-TING LIN ; SHEN-IUAN LIU | 2014 IEEE-EMBS International Conference on Biomedical and Health Informatics | 0 | 0 | |
1994 | Active-R sinusoidal oscillators using the CFA pole | Liu, S.-I.; Chang, C.-C.; Wu, D.-S.; SHEN-IUAN LIU | International Journal of Electronics | 33 | 26 | |
2006 | All-digital clock deskew buffer with variable duty cycles | Kao, S.-K.; Liu, S.-I.; SHEN-IUAN LIU | IEICE Transactions on Electronics | 6 | 6 | |
2016 | A Bang-Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques | Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 43 | 40 | |
1990 | Cascadable current-mode single CCII biquads | Liu, S.-I.; Tsao, H.-W.; Wu, J.; HEN-WAI TSAO | Electronics Letters | 56 | 51 | |
1993 | CCII-based fuzzy membership function and max/min circuits | Liu, S.-I.; Hwang, Y.-S.; Tsay, J.-H.; SHEN-IUAN LIU | Electronics Letters | 10 | 8 | |
2000 | Clock-deskew buffer using a SAR-controlled delay-locked loop | Dehng, G.-K.; Hsu, J.-M.; Yang, C.-Y.; Liu, S.-I.; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 87 | 70 | |
1995 | CMOS Analog Divider and Four-Quadrant Multiplier Using Pool Circuits | Liu, S.-I.; Chang, C.-C.; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 62 | 0 | |
1993 | CMOS four-quadrant multiplier using bias offset crosscoupled pairs | Liu, S.-I.; Hwang, Y.-S.; SHEN-IUAN LIU | Electronics Letters | 16 | 15 | |
1996 | A CMOS square-Law vector summation circuit | Liu, S.-I.; Chang, C.-C.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | 23 | 18 | |
1995 | CMOS Squarer and Four-Quadrant Multiplier | Liu, S.-I.; Hwang, Y.-S.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications | 22 | 0 | |
1995 | CMOS subthreshold four-quadrant multiplier based on unbalanced source-coupled pairs | Liu, S.-I.; Chang, C.-C.; SHEN-IUAN LIU | International Journal of Electronics | 19 | 17 | |
1991 | Current-mode oscillators using single current follower | Chen, J.-J.; Chen, C.-C.; HEN-WAI TSAO ; Liu, S.-I.; SHEN-IUAN LIU | Electronics Letters | 70 | 54 | |
1996 | Current-mode quadrature sinusoidal oscillator using single FTFN | Liu, S.-I.; Liao, Y.-H.; SHEN-IUAN LIU | International Journal of Electronics | 64 | 51 | |
2010 | Design of a CMOS low-power and low-voltage four-quadrant analog multiplier | Liu, W.; Liu, S.-I.; SHEN-IUAN LIU | Analog Integrated Circuits and Signal Processing | 30 | 25 | |
2018 | Development of 400 Gb/s optical transceivers for SMF based datacenter optical interconnect | Lee, S.-L.; Chen, J.; Liu, S.-I.; Yang, C.-F.; Tsao, H.-W.; Hsu, S.-H.; Lin, C.-C.; Yang, C.-L.; Zhang, Z.J.; Fu, K.-L.; Chung, L.W.; HEN-WAI TSAO ; SHEN-IUAN LIU | 2018 27th Wireless and Optical Communication Conference, WOCC 2018 | 0 | 0 | |
2015 | A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction | Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | 16 | 0 | |
2016 | A digital bang-bang phase-locked loop with bandwidth calibration | Chiang, C.-H.; Huang, C.-C.; Liu, S.-I.; SHEN-IUAN LIU | 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings | 4 | 0 | |
2017 | A digital MDLL using switched biasing technique to reduce low-frequency phase noise | Chiang, C.-H.; Huang, C.-C.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU | 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings | 0 | 0 | |
2013 | A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing | Lee, I.-T.; Chen, Y.-J.; Liu, S.-I.; Jou, C.-P.; Hsueh, F.-L.; Hsieh, H.-H.; SHEN-IUAN LIU | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 55 | 0 | |