公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
1994 | A 1.5 V 10 MHz BiCMOS quasi-digital vector modulator for wireless communication IC | Su, K.W.; Chen, Y.G.; Lai, C.S.; Kuo, J.B.; Wu, J.S.; Tso, H.W. | Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on | 0 | 0 | |
1993 | 1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture | Kuo, J.B.; Su, K.W.; Lou, J.H.; KuoJB | Electronics Letters | 2 | 0 | |
1995 | Accumulation-type vs. inversion-type: narrow channel effect in VLSI mesa-isolated fully-depleted ultra-thin SOI PMOS devices | Su, K.W.; Kuo, J.B. | SOI Conference, 1995. Proceedings., 1995 IEEE International | 0 | 0 | |
1996 | Analytical current conduction model for accumulation-mode SOI PMOS devices | Su, K.W.; Kuo, J.B. | Simulation of Semiconductor Processes and Devices, 1996. SISPAD 96. 1996 International Conference on | | | |
1995 | An analytical delayed-turn-off model for 6H-SiC buried-channel NMOS devices considering incomplete ionization | Su, K.W.; Kuo, J.B. | Solid-State and Integrated Circuit Technology, 1995 4th International Conference on | 0 | 0 | |
1994 | A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit | Su, K.W.; Lou, J.H.; KuoJB | IEEE International Symposium on Circuits and Systems, 1994. ISCAS '94 | 5 | 0 | |
1997 | Compact current model for mesa-isolated fully-depleted ultrathin SOI NMOS devices considering sidewall-related narrow channel effects | Kuo, J.B.; Su, K.W.; KuoJB | IEEE International SOI Conference | 0 | 0 | |
1994 | Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI | Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB | Custom Integrated Circuits Conference, 1994 | 0 | 0 | |
2006 | Generation of hydrocarbon gases and CO2 from a humic coal: Experimental study on the effect of water, minerals and transition-metals | Su, K.W.; Shen, J.C.; Chang, Y.J.; Huang*, W.L. | Organic Geochemistry | | | |
1995 | A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems | Kuo, J.B.; Lou, J.H.; Su, K.W.; KuoJB | ASIC Conference and Exhibit, 1995. | 0 | 0 | |