公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2002 | A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture | Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan | 2002 IEEE Asia-Pacific Conference on ASIC | 2 | 0 | |
2002 | A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay | Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan | Custom Integrated Circuits Conference, 2002 | 0 | 0 | |
2003 | A Spread-Spectrum Clock Generator With Triangular Modulation | Chang, Hsiang-Hui; Hua, I-Hui; Liu, Shen-Iuan | IEEE Journal of Solid-State Circuits | 102 | 85 | |
2005 | A wide-range and fast-locking all-digital cycle-controlled delay-locked loop | Chang, Hsiang-Hui; Liu, Shen-Iuan | IEEE Journal of Solid-State Circuits | 73 | 66 | |
2002 | A wide-range and fixed latency of one clock cycle delay-locked loop | Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
2004 | CMOS數位/類比式延遲鎖相迴路之設計與應用 | 張湘輝; Chang, Hsiang-Hui | | | | |
2003 | Low jitter Butterworth delay-locked loops | Chang, Hsiang-Hui; Sun, Chih-Hao; Liu, Shen-Iuan | 2003 Symposium on VLSI Circuits | 3 | 0 | |