| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
|---|---|---|---|---|---|---|
| 2009 | A False-Path Aware Formal Static Timing Analyzer Considering Simultaneous Input Transitions | Shih-Heng Tsai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | IEEE/ACM Design Automation Conference (DAC) | 6 | ||
| 2011 | A Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing Optimization | Shao-Lun Huang; Chi-An Wu; Kai-Fu Tang; Chang-Hong Hsu; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 13 | 0 | |
| 2010 | A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques | Bo-Han Wu; Chun-Ju Yang; Chung-Yang (Ric) Huang; Jie-Hong (Rol; ) Jiang; CHUNG-YANG HUANG ; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | 32 | 0 | |
| 2010 | A Unified Multi-Corner Multi-Mode Static Timing Analysis Engine | Chin-Chia Nien; Shih-Heng Tsai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 5 | 0 | |
| 2010 | Automatic Constraint Generation for Guided Random Simulation | Hu-Hsi Yeh; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 8 | 0 | |
| 2010 | Formal Deadlock Checking on High-Level SystemC Designs | Chun-Nan Chou; Chang-Hong Hsu; Yueh-Tung Chao; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | 9 | 0 | |
| 2008 | Improving Constant-Coefficient Multiplier Verification by Partial Product Identification | Chao-Yue (Colby) Lai; Chung-Yang (Ric) Huang; Kei-Yong Khoo; CHUNG-YANG HUANG | Design Automation and Test in Europe (DATE) | 5 | 0 | |
| 2009 | Interpolant Generation without Constructing Resolution Graph | Chih-Jen Hsu; Shao-Lun Huang; Chia-An Wu; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | 3 | ||
| 2003 | Non-Assignable Signal Support During Formal Verification Of Circuit Designs | Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | ||||
| 2007 | QuteIP: An IP Qualification Framework for System on Chip | Hsing-Chih Hung; Chi-Wen Chang; Tin-Hao Lin; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | IEEE SoC Conference (SOCC) | 1 | 0 | |
| 2007 | QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure | Chi-An Wu; Ting-Hao Lin; Chih-Chun Lee; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | Design Automation and Test in Europe (DATE) Conference | 11 | 0 | |
| 2011 | SoC HW/SW Verification and Validation | Chung-Yang (Ric) Huang; Yu-Fan Yin; Chih-Jen Hsu; Thomas B. Huang; Ting-Mao Chang; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 33 | 0 | |
| 2006 | Solving Constraint Satisfiability Problem For Automatic Generation of Design Verification Vectors | Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | ||||
| 2011 | Speeding Up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method | Yu-Fu Yeh; Chung-Yang (Ric) Huang; Chi-An Wu; Hsin-Cheng Lin; CHUNG-YANG HUANG | ACM/IEEE Design, Automation, and Test in Europe (DATE) conference | 1 | ||
| 2008 | Speeding Up SoC Virtual Platform Simulation by Data-Dependency Aware Virtual Synchronization | Kuen-Huei Lin; Siao-Jie Cai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | International SoC Design Conference (ISoCC) | 1 | 0 | |
| 2010 | Speeding Up SoC Virtual Platform Simulation by Data-Dependency-Aware Synchronization and Scheduling | Kuen-Huei Lin; Siao-Jie Cai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 3 | 0 | |
| 2010 | To SAT or Not to SAT: Scalable Exploration of Functional Dependency | Jie-Hong R. Jiang; Chih-Chun Lee; Alan Mishchenko; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG ; JIE-HONG JIANG | IEEE Transactions on Computers (TCOMP) | 21 | 16 |
