公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
1994 | Design and VLSI implementation of real-time weighted median filters | Chen, Chun-Te; Chen, Liang-Gee; Chiueh, Tzi-Dar; Hsiao, Jue-Hsuan; LIANG-GEE CHEN | IEEE Asia-Pacific Conference on Circuits and Systems | | | |
1994 | Design and VLSI implementation of real-time weighted median filters | Chen, Chun-Te; Chen, Liang-Gee ; Chiueh, Tzi-Dar ; Hsiao, Jue-Hsuan | IEEE Asia-Pacific Conference on Circuits and Systems, 1994. APCCAS '94 | 0 | 0 | |
1994 | An efficient pipelined VLSI implementation of rank order filter | Chen, Chun-Ta; Chen, Liang-Gee; Chiueh, Tzi-Dar ; Hsiao, Jue-Hsuan | 1994 International Symposium on Speech, Image Processing and Neural Networks, ISSIPNN '94 | 3 | 0 | |
1995 | Hardware-oriented design for weighted median filters | Chen, Chun-Te; Chen, Liang-Gee; Hsiao, Jue-Hsuan; LIANG-GEE CHEN | Asia and South Pacific Design Automation Conference, ASP-DAC | | | |
1995 | A hardware-oriented design for weighted median filters | Chen, Chun-Te; Chen, Liang-Gee ; Hsiao, Jue-Hsuan | Asian and South Pacific Design Automation Conference, IFIP International Conference on Hardware Description Languages and IFIP International Conference on Very Large Scale Integration, ASP-DAC '95/CHDL '95/VLSI '95 | 0 | 0 | |
1995 | A hardware-oriented design for weighted median filters. | Chen, Chun-Te; Chen, Liang-Gee; Hsiao, Jue-Hsuan; LIANG-GEE CHEN | Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995 | | | |
1994 | High throughput CORDIC-based systolic array design for the discrete cosine transform | Hsiao, Jue-Hsuan; Chen, Liang-Gee ; Chiueh, Tzi-Dar ; LIANG-GEE CHEN | 1994 IEEE International Symposium on Circuits and Systems, 1994. ISCAS '94., | 0 | 0 | |
1994 | High throughput CORDIC-based systolic array design for the discrete cosine transform | Hsiao, Jue-Hsuan; Chen, Liang-Gee; Chiueh, Tzi-Dar; Chen, Chun-Te; LIANG-GEE CHEN | IEEE International Symposium on Circuits and Systems | | | |