公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2012 | A linear 4- element model of VRM - characteristics, practical uses and limitations | E. H.-K. Hsiung; Y.-L. Li; R.-B. Wu; T. Su; Y.-S. Cheng; K.-B. Wu; RUEY-BEEI WU | IEEE Electrical Design for Advanced Packaging and Systems Symposium | 6 | 0 | |
2014 | A novel noise mitigation design for TSV-to-device coupling using power distribution network | C.-P. Chang; M.-K. Kang; T.-Y. Huang; K.-B. Wu; R.-B. Wu; RUEY-BEEI WU | IEEE 23rd Topical Meeting on Electrical Performance of Electronic Packaging and Systems | 0 | 0 | |
2006 | An efficient and flexible modeling for power/ground planes | K.-B. Wu; G.-H. Shiue; W.-D. Guo; C.-M. Lin; R.-B. Wu; RUEY-BEEI WU | 14th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP | 1 | 0 | |
2014 | Artificial neural network modeling for extrinsic capacitance of FinFET | W.-C. Chen; C.-P. Chang; M.-K. Kang; T.-Y. Huang; K.-B. Wu; R.-B. Wu; RUEY-BEEI WU | IEEE 23rd Topical Meeting on Electrical Performance of Electronic Packaging and Systems | 0 | 0 | |
2013 | Characterization of TSVs by cascaded daisy chains | Y.-C. Wu; K.-B. Wu; K.-Y. Yang; T.-Y. Huang; R.-B. Wu; RUEY-BEEI WU | IEEE 22nd Topical Meeting on Electrical Performance of Electronic Packaging and Systems | 0 | 0 | |
2008 | Delaunay–Voronoi Modeling of Power-Ground Planes With Source Port Correction | K.-B. Wu; G.-H. Shiue; W.-D. Guo; C.-M. Lin; R.-B. Wu; RUEY-BEEI WU | IEEE Transactions on Advanced Packaging | 43 | 33 | |
2009 | Design of shorting vias in alternative PCB planes for suppressing ground-bounce induced electromagnetic emission | K.-B. Wu; F.-S. Chang; R.-B. Wu; RUEY-BEEI WU | 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09 | 1 | 0 | |
2011 | Modeling and optimal design of shorting vias to suppress radiated emission in high-speed alternating PCB planes | K.-B. Wu; RUEY-BEEI WU ; D. De Zutter | IEEE Transactions on Components, Packaging and Manufacturing Technology | 14 | 10 | |
2018 | Novel RDL design of wafer-level packaging for signal/power integrity in LPDDR4 application | K.-B. Wu; T.-Y. Kuo; B. Hung; B. Lin; C. Peng; M.-T. Yang; R.-B. Wu; RUEY-BEEI WU | IEEE Transactions on Components, Packaging, and Manufacturing Technology | 10 | 6 | |
2011 | Optimal decoupling capacitors design for suppressing edge radiation of power/ground planes | K.-W. Li; K.-B. Wu; R.-B. Wu; RUEY-BEEI WU | IEEE 20th Topical Meeting on Electrical Performance of Electronic Packaging | 3 | 0 |