公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2010 | A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology | Yen-Chuan Huang; Tai-Cheng Lee; TAI-CHENG LEE | IEEE Journal of Solid-State Circuits | 19 | 18 | |
2010 | A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques | Yen-Chuang Huang; Tai-Cheng Lee; TAI-CHENG LEE | International Solid-State Circuit Conference | 20 | 18 | |
2009 | A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation | K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE | IEEE Journal of Solid-State Circuits | |||
2008 | An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits | Shih-Chun Lin; Tai-Cheng Lee; TAI-CHENG LEE | IEEE Aisan Solid-State Circuit Conference | 8 | 0 | |
2017 | Multi-mode VCSEL chip with high-Indium-density InGaAs/AlGaAs quantum-well pairs for QAM-OFDM in multi-mode fiber | Cheng-Ting Tsai; Chun-Yen Peng; Chun-Yen Wu; Shan-Fong Leong; Hsuan-Yun Kao; Huai-Yung Wang; You-Wei Chen; Zu-Kai Weng; Yu-Chieh Chi; Hao-Chung Kuo; Jian Jang Huang; Tai-Cheng Lee; Tien-Tsorng Shih; Jau-Ji Jou; Wood-Hi Cheng; Chao-Hsin Wu; Gong-Ru Lin; GONG-RU LIN ; 林恭如 | IEEE Journal of Quantum Electronics | 30 | 0 |