公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2006 | A 0.18μm probabilistic-based noise-tolerate circuit design and implementation with 28.7dB noise-immunity improvement | Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; AN-YEU(ANDY) WU | 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 | | | |
2007 | A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement | AN-YEU(ANDY) WU ; Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2007 IEEE Asian Solid-State Circuits Conference | | | |
2005 | A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications | AN-YEU(ANDY) WU ; Wey, I.-C.; Chang, L.-H.; Chen, Y.-G.; Chang, S.-H.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2007 | A clock-fault tolerant architecture and circuit for reliable nanoelectronics system | AN-YEU(ANDY) WU ; Ang, W.T.; Rao, H.F.; Yu, C.; Liu, J.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; Chen, J.; AN-YEU(ANDY) WU | 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007 | | | |
2004 | A fast and power-saving self-timed manchester carry-bypass adder for booth multiplier-accumulator design | AN-YEU(ANDY) WU ; Wey, I.-C.; Chow, H.-C.; Chen, Y.-G.; AN-YEU(ANDY) WU | 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | | | |
2005 | A high-speed scalable shift-register based on-chip serial communication design for SoC applications | AN-YEU(ANDY) WU ; Wey, I.-C.; Chen, Y.-G.; Wu, C.-T.; Wang, W.; AN-YEU(ANDY) WU | 2005 PhD Research in Microelectronics and Electronics | | | |
2006 | A new noise-tolerant dynamic circuit design with enhanced PDP performance under low SNR environment | AN-YEU(ANDY) WU ; Chen, Y.-G.; Wey, I.-C.; AN-YEU(ANDY) WU | 2006 IEEE Asian Solid-State Circuits Conference | | | |
2005 | A scalable DCO design for portable ADPLL designs | AN-YEU(ANDY) WU ; Wu, C.-T.; Wang, W.; Wey, I.-C.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2008 | An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation | AN-YEU(ANDY) WU ; Rao, H.; Chen, J.; Zhao, V.H.; Ang, W.T.; Wey, I.-C.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2008 | Design and analysis of isolated noise-tolerant (INT) technique in dynamic CMOS circuits | AN-YEU(ANDY) WU ; Wey, I.-C.; Chen, Y.-G.; AN-YEU(ANDY) WU | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | | | |
2007 | Dynamic channel flow control of networks-on-chip systems for high buffer efficiency | AN-YEU(ANDY) WU ; Wu, S.-T.; Chao, C.-H.; Wey, I.-C.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | | | |
2007 | Ensemble dependent matrix methodology for probabilistic-based fault-tolerant nanoscale circuit design | AN-YEU(ANDY) WU ; Rao, H.; Chen, J.; Yu, C.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2007 | Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules | AN-YEU(ANDY) WU ; Ye, J.-J.; Chen, Y.-G.; Wey, I.-C.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |