公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2003 | A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes | Wu, Cheng-Shing; Wu, An-Yeu; Lin, Chih-Hsiu; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | 64 | 42 | |
1995 | Algorithm-based low-power DSP system design: Methodology and verification | Wu, An-Yeu; Liu, K.J.Ray; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU | IEEE Workshop on VLSI Signal Processing | | | |
1995 | Algorithm-based low-power transform coding architectures | Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | | | |
1995 | Algorithm-based low-power transform coding architectures. | Wu, An-Yeu; Liu, K. J. Ray; AN-YEU(ANDY) WU | 1995 International Conference on Acoustics, Speech, and Signal Processing, ICASSP '95, Detroit, Michigan, USA, May 08-12, 1995 | 0 | 0 | |
1994 | Algorithms and architectures for split recursive least squares | Liu, K.J.Ray; Wu, An-Yeu; AN-YEU(ANDY) WU | IEEE Workshop on VLSI Signal Processing | 0 | 0 | |
1998 | Computationally efficient fast algorithm and architecture for the IFFT/FFT in DMT/OFDM systems | Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | | | |
1998 | Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology | Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | | | |
1998 | Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology. | Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU | Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98, Seattle, Washington, USA, May 12-15, 1998 | 15 | 0 | |
2004 | A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. | Jheng, Kai-Yuan; Jou, Shyh-Jye; Wu, An-Yeu; AN-YEU(ANDY) WU | Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004 | | | |
2000 | Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem | Leu, Jye-Jong; Wu, An-Yeu; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2000 | Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem. | Leu, Jye-Jong; Wu, An-Yeu; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings | 11 | 0 | |
2006 | DSP engine design for LINC wireless transmitter systems. | Jheng, Kai-Yuan; Wang, Yi-Chiuan; Wu, An-Yeu; HEN-WAI TSAO ; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece | 0 | 0 | |
2007 | Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. | Rao, Huifei; Chen, Jie; Yu, Changhong; Ang, Woon Tiong; Wey, I-Chyn; Wu, An-Yeu; Zhao, Hong; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA | 6 | 0 | |
1998 | Fast algorithm for reduced-complexity programmable DSP implementation of the IFFT/FFT in DMT systems | Wu, An-Yeu; Chan, Tsun-Shan; Wang, Bowen; AN-YEU(ANDY) WU | IEEE Global Telecommunications Conference | | | |
2001 | An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter. | Yu, Chi-Li; Wu, An-Yeu; AN-YEU(ANDY) WU | Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001 | 4 | 0 | |
2007 | Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. | Ye, Jhao-Ji; Chen, You-Gang; Wey, I-Chyn; Wu, An-Yeu; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA | 1 | 0 | |
1994 | Low-power and low-complexity DCT/IDCT VLSI architecture based on backward chebyshev recursion | Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
1994 | A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion. | Wu, An-Yeu; Liu, K. J. Ray; AN-YEU(ANDY) WU | 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994 | 0 | 0 | |
1996 | Low-power design methodology for DSP systems using multirate approach | Wu, An-Yeu; Ray Liu, K.J.; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2000 | Modified vector rotational CORDIC (MVR-CORDIC) algorithm and its application to FFT | Wu, Cheng-Shing; Wu, An-Yeu; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |