電力在現今社會中已成為一切工商業之母，發電廠所產生之電力需經由輸、配電線路傳送給各用戶。在目前日常生活之種種事物皆需依賴電力的情形下，穩定之電力輸送將攸關著國家社會之經濟成長與秩序之穩定。準確、快速且可靠的故障保護技術在現代的輸配電系統中是一項重要的要求，本計畫提出以一個可動態改變架構與學習能力的類神經網路，進行一系列共三年的研究計畫，計畫包含有(第一年)輸配電線路故障類別之波形辨識，(第二年)輸配電線路之故障定位，以及(第三年)具有強健性能可自我適應不斷變動之輸配電線路之故障類別辨識與自動定位晶片。本計畫採用的故障電壓電流資訊量測平台，為可提供準確的時間同步之訊號量測資訊之GPS-PMU平台，並且可以利用所量測得到之資料，利用小波分析技術以及動態連結類神經網路DSNN，進行波型之分析，進行故障偵測、故障類別的辨識與故障位置之定位。最後，本計畫將設計出一套小型且低成本之硬體晶片(利用Altera FPGA IC)，使之應用於實際電力系統時可更加節約與便利。本計畫之執行預計以三年分三階段進行，茲分述如下：
本計畫將使用自行開發的可動態自我適應的類神經網路進行故障定位技術研發，故初始必須收集到一定量的訓練資料，而這些訓練資料將必須包含各端點所量測得之電流數據，故障電流的下降與量測端點距離呈現一個等比級數的下降，這樣的關係可以利用統計方法中的Lowess regression或是cubic spline方式來進行故障電壓下降趨勢的波形建模。當故障電流比例與距量測端點之距離的迴歸曲線建模完成後，即可針對固定兩個(或更多)量測點之故障電流比例數據，將之輸入給動態連結是類神經網路，並且將資料庫中紀錄之確實故障位置作為輸出目標值，進行類神經網路之訓練，並在輸配電線路故障發生時，進行故障位置之預測與定位。
本年度將根據所研發之強健型輸配電線路故障偵測與故障種類辨識以及故障定位演算法，實現為獨立運作之硬體系統。本計畫擬採用Altera FPGA晶片進行演算法之硬體化實作與驗證。所擬研製的FPGA晶片中之組成電路，則可再細分為小波分析、統計特徵萃取，以及新式強健型類神經網路演算法執行電路，並可將運算處理結果輸出至控制面板上進行顯示。本年度計畫之FPGA內部程式設計，吾人將之規劃區分成A/D Bridge、LCD Controller、Bridge Controller、FLASH Controller和SRAM Controller五大區塊。本計畫所研製之Altera FPGA晶片將可成為一套可嵌入輸電線保護電驛系統之元件，或可製成一套手持型設備，可進行移動式監控與判定故障事件之器材。
At modern time, electricity power is the basis for development of industry and economy in every country. The electricity power was generated by power plants, and was transmitted to the client terminal through a very complex transmission network. Due to everything in our daily life works depending on the electricity power, maintaining the transmission network stable and reliable is essential to national security and economic growth. Developing an accurate, fast, and reliable fault protection technique is a very important task in modern power transmission system. In this proposal, we will prosecute this three-year research project based on a new neural network model (i.e., dynamically structuring neural network, DSNN) which has two primary features: deformable network structure, and adjustable learning capacity. The objectives of the first year and second year of this proposal are to develop a robust fault detector/fault classifier and fault locator based on DSNN, respectively. The final task of the last year is to develop a chip that is adaptive to the changing transmission network, and also capable of classifying and locating the type and location of faults on the transmission lines. In this proposal, all voltage and current data will be measured by a GPS-PMU platform, which provides synchronized time-tag for each measured data. By combining the wavelet transformation technique and DSNN, we can design an adaptive fault detection, fault classification, and location algorithm. Finally, this research project will implement the algorithm into an Altera FPGA IC with abilities of fault analysis, detection and location. Due to the lower cost of making an IC, it will make the power company has lesser doubts to apply the algorithm to the practical power transmission network. The three-year proposal is planning to carry out in the following three stages:
1. The first year:
In this stage, the project is planned to develop the fault detection and classification algorithms that can be utilized to protect the transposed/untransposed single/double- circuit transmission lines. A dynamically structuring neural network (DSNN) algorithm is to be developed and utilized to classify fault types on transmission lines. Because the developed DSNN-based protective relaying algorithm is adaptive to changes of transmission lines or multi-faults situations, the developed protective relaying system is suitable for long term usage. In this stage, a database and data mining system are planned to be established for systematically organizing measured fault data. Using the developed data mining system, the fault detection and classification algorithms can be trained more precisely and objectively. The performance of the proposed protective relaying algorithms will be evaluated by the fault data generated by EMTP/MATLAB Simulink. Using these fault detection and classification algorithms, the relay can achieve the single-pole reclosure function to promote the reliability, quality, and stability of the power system.
2. The second year:
In this year, we will use the developed DSNN to design fault location algorithm. At first, certain amount of measured data must be collected to form a training data set, and such data must contain the measured fault currents at various distances from a measurement terminal. Secondly, the relation of the measured fault currents versus measuring location will exhibits an inverse proportional relationship and can be modeled by statistic methods, such as Lowess regression or cubic spline. By using two or more fault currents estimated by the regression model at fixed positions as input of the adaptive neural network model, we can train the adaptive neural network model according to the knowledge stored in the training data set. After the training process has been completed, the adaptive neural network would be able to be utilized as a fault location estimator when fault currents were measured in the transmission network.
The third year:
In this stage, the fault detection, fault classification, and location algorithms developed in previously two stages are planned to be integrated and implemented into an IC. An Altera FPGA is planned to be utilized to design and verify the functions of the hardware implemented algorithms. The developed Altera FPGA ICs can be further classified into several subcircuits including wavelet analysis circuit, statistical characteristic extraction circuit, and several circuits for implementing DSNN-based algorithms. The internal programming design for FPGA ICs consists mainly of A/D bridge, LCD controller, bridge controller, FLASH controller, and SRAM controller. Integrating with other peripheral circuits and components, the implemented FPGA ICs can be integrated into a protective relaying system, or also can be putted in use of designing a small portable device, for transmission lines. Such a design can provide fault detection, fault classification, and location functions for more practical usage.
Keywords: Protective relaying, fault detection, fault classification, fault location, neural networks, FPGA prototype design.