Abstract
摘要:近年來,電子業最關注的議題,莫過於左右半導體業界成長數十載之莫爾定律(Moore’s law)即將走向終點。為延續後莫爾定律之半導體科技發展,產業界多有共識,將以發展3D-IC (Three-Dimensional Integrated Circuit) 結構為主要因應策略。相較於傳統2D-IC,此結構更具有輕薄短小、高工作性能、低耗能,甚至更低廉的製造成本等優勢。
晶片對接(Chip-to-chip bonding)技術為3D結構發展中非常關鍵的製程,其係使用微小銲料接點以進行晶片間之接合行為,是為極具潛力之接合方式。目前,先進封裝技術中所採用的微銲點尺寸大小約莫介於數微米之間。但在不久的將來,銲點尺寸可預期會再度縮小至次微米甚至奈米等級。然而,產學界對此類微小接點機械強度特性的瞭解卻相當有限。在文獻中幾乎未有任何相關報導,可見此課題具有相當廣闊的研究空間。本計畫之主要目的,在於建,以期樹立本研究團隊在該領域中之世界領導地位。
綜觀諸多目前研發中的3D-IC封裝技術,大多採用具有低熔點之金屬合金做為晶片間的連接橋樑。在3D-IC組件中,合金所承受之周遭環境與熱衝擊大致與傳統銲點無異。然,此兩者間最大的差異,在於3D-IC接點之體積甚小,導致接點中的銲料體積非常少。舉例來說,典型的3D-IC接點銲料體積約為1500μm3,僅為目前主流覆晶接點(Flip-chip joints)的1/300(以直徑為100μm的覆晶接點為例)。因此,由銲料體積效應所導致的界面反應與機械特性等相關課題將隨之而生。其中,最主要的挑戰,即是微接點內部銲料可能在晶片製造或是使用過程中完全轉變成介金屬化合物(Intermetallic compounds)。介金屬質地硬且脆,當接點中充滿介金屬化合物時可能會使接點產生諸多獨特的性質。
由此判斷,決定3D-IC微接點性質的關鍵不再僅是銲料本身,也與其所生成之介金屬其性質關係密切。然而,目前各界對3D-IC微接點之特性所知有限,過去文獻中與其相關之研究亦是寥寥可數。有鑑於此,本計畫擬將深入探究3D-IC微接點特性並釐清潛在影響可靠度之因素。諸如微接點內介金屬成長與分布特徵、習用之Ni、Au表面處理層適用與否,以及接點內部組織變化所誘發之體積改變效應等。本計畫之另一目的在於根據接點特性研究成果,評估目前經常使用之In、Sn等合金是否適用於3D-IC封裝,進而嘗試開發新穎之3D-IC微接點用材料。
Abstract: Imminent ending of Moore’s law is the most critical issue threatening the continued development of semiconductor industry. The strategy of consensus, as stated in the 2009 International Technology Roadmap for Semiconductors, in order to go beyond Moore’s law is through the 3D-IC (Three-Dimensional Integrated Circuit) architecture. The benefits of 3D-IC integration include higher performance, reduced power requirement, smaller size, and eventually lower cost than conventional 2D-IC.
Chip-to-chip bonding is one of the vital processes enabling the implementation of 3D-IC architecture. Among various chip-to-chip bonding techniques, solder micro bumping is considered as the most promising one. Current state-of-the-art solder micro bumping has a diameter of a few microns, and sub-micron or nano joining is really not very far ahead in the future. This rapid shrinkage in joint size, unfortunately, is not accompanied by our concurrent advance in fundamental understanding of the mechanical strength of such joints. There is essentially no prior study in this area, and this field is a wide open research area. The objectives of the proposed project are to establish a fundamental knowledge concerning mechanical performance for joints of such small size scale and to devise a theoretical framework for our understanding of such behaviors. The overall goal is to become the world-wide leading research group in this area.
In many of the 3D-IC packaging schemes under development today, solders are the materials of choice for enabling die-to-die connections. While solders in 3D-IC packages experience an environment and thermal budget similar to those of their counterparts in outer-level electronic packages, they are subject to some conditions that are unique to 3D-IC packaging. One such condition is the solder volume that is much smaller in 3D-IC packages as compared to solder joints in outer levels of packages. The typical solder volume of a 3D-IC is about 1500μm3, which is only 1/300 that of the 100-μm-diameter flip-chip solder joint of. Many new issues of interfacial reactions and mechanical properties arise due to this size effect. One well-known effect of a small solder volume is that the entire solder layer might be completely transformed into intermetallic compounds (IMCs) during the operation, or fabrication of a device. As IMCs tend to be hard and brittle, a solder joint composed entirely of IMCs might have peculiar, if not inferior, mechanical properties. Accordingly, the mechanical properties of micro joints do not depend on the mechanical properties of solder alone, but also depend on those of IMCs. Again, there is very limited open literature available on the characteristics of such type of joints. It is our intention to initiate a systematic study to fill this literature void.
Keyword(s)
三維積體電路
晶片對接
銲料
穿晶通孔
界面反應
Three-dimensional integrated circuit
Chip-to-chip bonding
Solder
Through silicon vias
Interfacial reaction