摘要:7nm–5nm 世代預計量產時間點約是2024-2027年,該世代的Vdd=0.5V、 Ion(N)=2900 uA/um、Ion(P)=2600uA/um、Ioff=100nA/um (國際半導體技術藍圖2011 ITRS/PIDS) !! 回顧90nm世代的strain-enhanced mobility技術,45nm世代的high k/metal世代,22nm世代的FinFET,使得研發落後的公司逐漸淘汰,如同DRAM一樣,台灣因無自我技術,而遭淘汰,許多CMOS公司亦退出市場,如TI、Motorala…。在台灣三家主要的foundry(tsmc、UMC及Vangard)之營收在2012預期分列第一(16.7B USD),第三(3.8B USD),第八(0.6B USD)。為了要維持技術的競爭及菁英人才的培育,台積電與台大經過嚴密的協商,將以7-5nm技術世代做為合作研發主軸,希望在300B美金以上的市場中,為台灣未來二十年奠下成功及扎實的基礎。矽基互補式金氧半場效電晶體已逼近了物理與技術上的極限,進一步於矽基元件上的微縮將難以帶來更好的元件性能。根據 ITRS,為了滿足次世代CMOS之提升通道載子傳輸速率以及降低元件功率損耗等要求,目前半導體產業界與學術界一致認為,未來必須要採用新的元件結構並引進高介電常數氧化物/金屬閘極技術於鍺(PFET)以及三五族化合物砷化銦鎵(NFET)等具有高載子遷移率之通道材料,元件結構為gate-all-around (GAA)/nanowire (pn junction, TFET, junctionless,以符合7奈米節點以下的CMOS之規格需求。將通道材料整合於矽基板上的革命性技術,將可以大幅領先現有以矽為主的半導體技術。超越7nm世代的技術,目標為:高Ion,低Ioff,low Vdd (power),所要考量的方向為:(1) injection velocoty/mobility的提升:增加Ion,(2) electrostatic control: GAA,double GAA,減少Ioff及Subthreshold Slope (SS)與(3) 減少parasitic S/D and capacitance。反應到製程技術的需求為:(1) 5-7nm的litho, 降低line edge roughness,(2) high mobility channel的成長(III-V,Ge),(3) 金屬/半導體barrier height control及active doping control,(4) gate stack及interface與(5) etching後的surface roughese降低。要打破物理極限,就要對物理有深入的了解,要製作高效能又低成本的IC,就必須對製程、設計方法和設計自動化有極大的創新。因此台大團隊結合電機系、物理系、材料系、機械系、化學系…眾志成城為未來半導體研發打破極限。
整理文獻上所有相關的理論與實驗,這是台大師生最拿手之處。將錯的排除,對的整理,分門別類了解現在的狀況,以理論分析及模擬了解技術之可能性,再做必要實驗以佐證想法。找出可能用到的技術,與現在無法達到的技術瓶頸。以ITRS之 III-V NFET/Ge PFET 為基礎,III-V NFET+PFET 或Ge PFET+NFET (2011 ITRS/ERD/ERM)為創新、2D material (silicene, germanece, transition metal dichalcogenides such as WSe2, MoS2..) FETs為挑戰。其他元件如CNT FET、 GNR FET、Spin FET 、iMOS、Atomic switch, Mott FET, Ferroelectric NC FET、spin wave、nano magnetic、BISFET …(ITRS/ERD) ,研判成功機率較小,暫不考慮, 但會注意。
隨著半導體元件不斷的微縮,半導體專家們已意識到新的元件必須搭配合適當的電路設計方法,方能發揮最大效能 。這可由最近的國際會議,如IEDM及VLSI Symposium等,均討論有關device and circuit co-design的議題,得到確認。展望未來,元件與電路設計方法的同時最佳化是必要的。當代的元件特性限制已讓設計變得異常困難,未來即便研發出奈米元件,如只能使用傳統的電路設計方法,很可能無法達到產品要求。更有效的電路設計方法與設計自動化工具必須被發明,才可將奈米元件的高密度好處,充分發揮,而其缺點不致於影響預期的功能。
Abstract: The production for the 7-5nm generation is about to happen during 2024-2027, where the performance of devices is Vdd = 0.5V, Ion (N) = 2900 uA/um, Ion (P) = 2600 uA/um, Ioff = 100nA/um (see the International Technology Roadmap for Semiconductors 2011 ITRS / PIDS). From the experience of the technologies of strain-enhanced mobility at the 90 nm node, the high-k/metal gate at the 45 nm node, and FinFET at the 22 nm node, those companies with lagging research and development capacity usually failed to catch up and were phased out from the market; for example, many DRAM and CMOS companies, such as Taiwanese DRAM companies, TI, Motorala, etc.
The three major Taiwanese foundries, TSMC, UMC, and Vangard, have their expected 2012 respective revenues at USD 16.7B, USD 3.8B, and USD 0.6B, ranking them the 1st, 3rd, and 8th largest foundries in the world. In order to maintain the competitivity and cultivate elite talents, TSMC and NTU will closely cooperate with each other for the research and development of the 7-5 nm technology. With this cooperation, we hope to lay a solid foundation for the continuing success of the Taiwan semiconductor industry in this USD 300B+ market in the next two decades.
Silicon complementary metal oxide semiconductor field effect transistors (CMOS) have been approaching the physical and technical limits. It will be difficult for a further miniature of silicon CMOS to achieve better device performance. According to the ITRS roadmap, in order to meet the requirements of the next-generation CMOS such as increasing the transport velocity of a carrier in the channel and reducing the requirements of power loss, the semiconductor industry and academia agreed that the future devices must use new device structures such as gate-all-around (GAA)/nanowire (pn junction, TFET, junctionless) and high dielectric constant oxide/metal gate technology on high carrier mobility channel materials, such as germanium (pFETs) and III-V compounds arsenide, indium gallium (InAs and InSb nFET), to comply with the specification requirements of CMOS at the 7 nm node.
The revolutionary technology with the integration of the channel material deposited on Si substrates can be significantly ahead of the existing silicon-based semiconductor technology. Beyond the 7nm technology, the goals are high Ion, low Ioff, low Vdd (power), and the desired directions are as follows: (1) Increase injection velocity/mobility: increase Ion; (2) Imporve electrostatic control: use GAA and/or double gate, reduce Ioff and subthreshold slope (SS.); and (3) Reduce parasitic S/D and capacitance. The corresponding requirements of process technology are as follows: (1) 5-7nm litho for lower line edge roughness, (2) growth of high mobility channels (III-V, Ge), (3) control of metal/semiconductor barrier height and active doping, (4) gate stack and the interface, and (5) reduction of etching after surface roughness.
To break the physical limits, it is necessary to have a deep understanding of the physics and design automation/methodology for fabricating high-performance and low-cost ICs with great innovation. Our team with experts with the backgrounds of electrical engineering, physics, materials science, mechanical engineering, and chemistry, etc. will work hand-in-hand to break the limit for the future semiconductor research and development.
Our team researchers are good at consolidating all relevant theory and experiments in the literature. With the literature survey, we will first differentiate correct results from the wrong ones to better understand the current state-of-the-art technologies. With our future theoretical analysis, simulation, and experiments, we would better understand the technology trends, identify promising technologies, and aviod technical bottlenecks. We will first work on III-V NFET / Ge PFET based on the ITRS roadmap, then on III-V NFET + PFET or Ge PFET + NFET (2011 ITRS / ERD / ERM), and finally on 2D materials (silicone, germanece transition metal dichalcogenides such as WSe2, MoS2, etc.) FETs. We will also pay attention to the development of other components, such as CNT FET, GNR FET, spin FET, iMOS, atomic switch, Mott FET, Ferroelectric NC FET, spin wave, nano magnetic, BISFET (ITRS / ERD), despite their smaller chances of success.
As the continuing miniature of semiconductor devices, researchers observed that it is important to develop effective design automation tools and methodology for better use of new devices, which can be justified thorugh the emerging topics on device and circuit co-design at premier convferences such as IEDM and VLSI Synmposium. For future production needs, it is essential to consider the co-optimization of devices, circuit design, and design automation to handle the complicated constraints arising in new devices.