摘要:根據國際半導體技術藍圖,為了滿足次世代互補式金氧半場效電晶體之提升通道載子傳輸速率以及降低元件功率損耗等要求,勢必需要採用新的元件結構和鍺以及三五族化合物砷化銦鎵等具有高載子遷移率之通道材料以符合15奈米節點以下的互補式金氧半場效電晶體之規格需求。預期將於大約4個世代之後實行此一整合高介電質材料與金屬閘極於高載子遷移率半導體與矽之混合基板之嶄新技術。此技術之實行將開發更快速之元件並成功解決所謂「性能差距」(performance gap)的缺失。除此之外,相較於傳統材料-矽,砷化銦鎵與鍺在低操作電壓方面提供了明顯的優勢,預期將可大幅降低能源消耗率。
近期我們成功地以自對準製程實現了反轉通道式Al2O3/GGO/In0.53Ga0.47As金氧半場效電晶體,其汲極電流與轉導值皆創下了世界紀錄。如此成果不僅是過去40年來三五族金氧半場效電晶體的一大突破,更證明了使用三五族材料於15奈米節點以下之互補式金氧半場效電晶體的可行性。然而,若欲實現三五族金氧半場效電晶體於高速以及低功率元件之應用,我們仍然須克服許多的科學與技術上之挑戰,除了需完全地了解及掌控砷化銦鎵及鍺的基本性質外,關於它們對元件特性的影響也將是未來製程整合以及量產的關鍵因素。除熱穩定性之外,電子傳輸特性,特別是如何利用高介電材料鈍化其和半導體界面的電活性缺陷以達到盡可能最低的介面能階密度,在在都是身為基礎物理及材料研究者的巨大挑戰。
立基於過去與學術界(國立清華大學,國立台灣大學,國立交通大學,國立中央大學, 以及國立中山大學)以及國家實驗室(國家奈米元件實驗室與國家同步輻射研究中心)之間的密切合作,我們已經組織了一個陣容堅強的研究團隊。敝團隊研擬三大子題研究:(1)高介電材料成長與電性分析,(2)自對準反轉通道或量子井結構之砷化銦鎵(以及鍺)金氧半場效電晶體,以及(3)砷化銦鎵(以及鍺)於矽基板上之整合等關鍵領域進行以下具有競爭力的基礎研發計畫。為了發展必要之科學基礎,並且在履行2015-2018年量產之前建立一個可在未來五年內實行之成熟技術平台,這些目標刻不容緩地需要被付諸執行:子題(1-1)項目:將用臨場原子層沉積技術於分子束磊晶製備之鍺以及三五族半導體之平整表面上成長高介電氧化物,藉此了解解除費米能階紮釘的機制,並由臨場XPS、STM和STS輔助分析,以獲得具最少界面缺陷密度之最佳原子層沉積高介電氧化物與三五族(鍺)之氧化物/半導體界面結構。子題(1-2) 項目:以變溫電導量測及準靜態電容-電壓量測等廣泛的電性分析對缺陷密度以及費米能階移動之自由度進行定量化之分析,並以雜訊量測 (1/f noise)來探討缺陷輔助式穿隧和氧化物薄膜崩潰前的退化,以深入了解普遍存在於高介電氧化物之電荷攫取特性。子題(2-1) 項目:欲製造可用於高速、高頻,以及低功率元件之具有低關閉態漏電流、高導通電流以及高轉導值之自對準反轉通道砷化銦鎵(以及鍺)金氧半場效電晶體,並最小化次臨界擺幅;子題(2-2) 項目:製造與模擬次微米元件以了解短通道效應。子題(3-1) 項目:將成長無缺陷之鍺(矽鍺)於矽基板; 子題(3-2) 項目:成長砷化銦鎵於鍺/矽基板。
Abstract: As driven by continual demands of faster speed and reducing power dissipation for the next-generation CMOS technology, new device structures and high carrier-mobility channel materials such as Ge and III–V compound InGaAs may be needed, according to the ITRS roadmap, to meet the power and performance specifications of the 15 nm CMOS node and beyond. The new technology of high- plus metal gate on InGaAs and Ge hybrid with Si may be four chip generations away, leading to faster devices and closing the so-called “performance gap”. Furthermore, InGaAs and Ge offer distinct advantages over Si at low supply voltages, thus greatly reducing power consumptions.
We have achieved world record high drain current (ID) and transconductance (G¬m) in the self-aligned inversion-channel Al2O3/GGO/In0.53Ga0.47As MOSFET, not only a breakthrough for III-V MOSFET in past four decades, but also a feasibility proof for using III-V materials for CMOS beyond the 15 nm node. However, there are still many scientific and technical challenges needed to be overcome to make III-V MOSFETs viable for future high speed and low power applications. The basic properties of InGaAs, Ge MOS structures with high-κ dielectrics and their impacts on the device performance will have to be fully understood and under control, as the prerequisites to allow for process integration and full-scale manufacturing. In addition to thermal stability, electronic transport properties, and especially the passivation of electronically active defects at the high-κ/semiconductor interface in achieving very low interfacial densities of states, are enormous challenges to basic physics and materials researchers.
Based the past close collaboration among academics (NTHU, NTU, NCTU, NCU, and NSYSU) and national laboratories (NDL and NSRRC), we have built a strong team, and propose to undertake the following competitive fundamental research and development programs in three key areas on (I) further reduction of interfacial densities of states Dit in high ’s on InGaAs and Ge, (II) high-performance, self-aligned inversion-channel InGaAs and Ge MOSFET’s for “Green” IC, and (III) growth and integration of InGaAs and Ge on Si; these are critically needed and urgently called for to develop the essential scientific base and to build a viable technology platform to be matured in next five years before manufacture implementation in year 2015 - 2018: there are three sections on sub-proposal (I), with section (I-A) performing growth of high oxides on pristine MBE-grown surfaces of Ge and InGaAs using in-situ ALD and in-situ ALD/MBE; section (I-B) to acquire understandings of the Fermi level unpinning mechanism and optimization of interfacial structures of ALD and ALD/MBE high- oxides/III-V(Ge) using in-situ XPS, and in-situ STM/STS in order to achieve minimal interfacial state density; section (I-C) to study comprehensive electrical characterizations of the high MOS gate stacks by temperature dependent conductance, quasi-static CV measurements to quantify defect density and free Fermi level movement. For deeper understanding of charge trappings common of high oxides, 1/f noise will be utilized to probe trap assisted tunneling and degradations in thin oxides prior to breakdown. On sub-proposal (II), section (II-A) performs the fabrication of self-aligned inversion-channel InGaAs n-MOSFETs with emphasis on low off-state leakage currents, high on-state current drivability, high transconductance for high-speed, high-frequency, and low-power devices, and minimization of sub-threshold swing; the efforts will also be extended to the fabrication and simulation of sub-micron and nano-meter devices for understanding short-channel effects; section (II-B) on Ge p-MOSFETs; and section (II-C) covers the integration of n- and p-channel transistors, device simulation and high-frequency RF characteristics. Sup- proposal (III) devotes to the growth of defect-free Ge (SiGe) on Si in section (III-A); and section (III-B) deals with the growth of InGaAs on Ge/Si substrates.