研究成果

第 1 到 123 筆結果，共 123 筆。

公開日期標題作者來源出版物scopusWOS全文
120242.6 A 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication SystemsLee, Tang; Chen, Ting Yang; I-HSUAN LIU; CHIA-HSIANG YANG Digest of Technical Papers - IEEE International Solid-State Circuits Conference
2202430.4 A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation OptimizationChu, Yi Chen; Lin, Yu Cheng; Lo, Yu Chen; CHIA-HSIANG YANG Digest of Technical Papers - IEEE International Solid-State Circuits Conference
32023Clinical utility of anal sphincter relaxation integral in water-perfused and solid-state high-resolution anorectal manometryJIA-FENG WU ; Lin, Yu-Cheng; CHIA-HSIANG YANG ; PING-HUEI TSENG ; I-JUNG TSAI ; WEN-HSI LIN ; WEN-MING HSU Journal of the Formosan Medical Association = Taiwan yi zhi10
42023An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT DevicesYu, Sheng Jung; Lee, Yu Chi; Lin, Liang Hsin; CHIA-HSIANG YANG IEEE Journal of Solid-State Circuits00
52023A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution AcceleratorShen, Hsueh Yen; Lee, Yu Chi; Tong, Tzu Wei; CHIA-HSIANG YANG IEEE Journal of Solid-State Circuits00
62023A 73.8K Inference/mJ SVM Learning Accelerator for Brain Pattern RecognitionTong, Tzu Wei; Hsieh, Yi Yen; Chen, Tai Jung; CHIA-HSIANG YANG 2023 IEEE Asian Solid-State Circuits Conference, A-SSCC 2023
72023A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation SequencingChen, Yen Lung; Yang, Chung Hsuan; Wu, Yi Chung; Lee, Chao Hsi; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Chi Shi; Hung, Jui Hung; CHIA-HSIANG YANG Digest of Technical Papers - IEEE International Solid-State Circuits Conference00
82023A 169mW Fully-Integrated Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held DevicesLo, Yi Lin; Lo, Yu Chen; CHIA-HSIANG YANG Digest of Technical Papers - Symposium on VLSI Technology00
92023A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural InterfacingLin, Liang Hsin; Fu, Zih Sing; Chen, Po Shao; Yang, Bo Yin; CHIA-HSIANG YANG Digest of Technical Papers - Symposium on VLSI Technology00
102023An FM-index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-end Short-read MappingYang, Chung Hsuan; Wu, Yi Chung; Chen, Yen Lung; Lee, Chao Hsi; Hung, Jui Hung; CHIA-HSIANG YANG IEEE Transactions on Biomedical Circuits and Systems00
112023A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive SensingLin, Yu Cheng; Park, Chanmin; Zhao, Wenda; Sun, Nan; Chae, Youngcheol; CHIA-HSIANG YANG Digest of Technical Papers - Symposium on VLSI Technology00
122023A 96.2-nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure PredictionHsieh, Yi Yen; Lin, Yu Cheng; CHIA-HSIANG YANG IEEE Journal of Solid-State Circuits11
132023A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image DeblurringChen, Po Shao; Chen, Yen Lung; Lee, Yu Chi; Fu, Zih Sing; CHIA-HSIANG YANG IEEE Journal of Solid-State Circuits
142023A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic DataflowDu, Cheng Yan; Tsai, Chieh Fu; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Chi Shi; CHIA-HSIANG YANG Digest of Technical Papers - IEEE International Solid-State Circuits Conference00
152022Achieving Accurate Automatic Sleep Apnea/Hypopnea Syndrome Assessment Using Nasal Pressure SignalYing-Sheng Lin; Yi-Pao Wu; Yi-Chung Wu; PEI-LIN LEE ; CHIA-HSIANG YANG IEEE Journal of Biomedical and Health Informatics22
162022A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented RealityHuang, Wen Cong; Lin, I. Ting; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Chi Shi; CHIA-HSIANG YANG Digest of Technical Papers - Symposium on VLSI Technology10
172022Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network CompressionKao, Chen Chien; Hsieh, Yi Yen; Chen, Chao Hung; CHIA-HSIANG YANG Midwest Symposium on Circuits and Systems10
182022A 75.6M Base-pairs/s FPGA Accelerator for FM-index Based Paired-end Short-Read MappingYang, Chung Hsuan; Wu, Yi Chung; Chen, Yen Lung; Lee, Chao Hsi; Hung, Jui Hung; CHIA-HSIANG YANG 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings00
192022A 44.3mW 62.4fps Hyperspectral Image Processor for MAV Remote SensingLo, Yu Chen; Wu, Yi Chung; CHIA-HSIANG YANG Digest of Technical Papers - Symposium on VLSI Technology00
202022CAS Research and Teaching Activities in Taiwan [CAS in the World]Chang, Robert Chen Hao; Hwang, Yin Tsung; Lin, Yuan Pei; CHIA-HSIANG YANG IEEE Circuits and Systems Magazine00
212022A 1.3mW Speech-to-Text Accelerator with Bidirectional Light Gated Recurrent Units for Edge AITsai, Yu Hsuan; YI-CHENG LIN; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Shi Hao; Chen, Chi Shi; CHIA-HSIANG YANG 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings00
222022A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device TrainingFu, Zih Sing; Lee, Yu Chi; Park, Alex; CHIA-HSIANG YANG Digest of Technical Papers - Symposium on VLSI Technology30
232022A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure PredictionHsieh Y.-Y; Lin Y.-C; CHIA-HSIANG YANG Digest of Technical Papers - IEEE International Solid-State Circuits Conference70
242021Bolus transit of upper esophageal sphincter on high-resolution impedance manometry study correlate with the laryngopharyngeal reflux symptomsJIA-FENG WU ; WEI-CHUNG HSU ; I-JUNG TSAI ; Tong, TW; Lin, YC; CHIA-HSIANG YANG ; PING-HUEI TSENG SCIENTIFIC REPORTS22
252021Design of a Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its in Vivo VerificationLiu C.-H; Wu, Chung-Yu; Ker, Ming-Dou; Liu, Chien-Hao ; Hung, Chung-Chih; Yang, Chia-Hsiang ; Lee, Chia-Fone; Chang, Po-Chih; Tu, Yen-Fu; Tang, Li-Yang; Chen, Ching-Yuan; CHIEN-HAO LIU IEEE Journal of Solid-State Circuits128
262021A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human GenomeChen Y.-L; Chang B.-Y; CHIA-HSIANG YANG ; TZI-DAR CHIUEH IEEE Transactions on Parallel and Distributed Systems815
272021A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation SequencingCHIA-HSIANG YANG IEEE Journal of Solid-State Circuits
282021A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT DevicesCHIA-HSIANG YANG ; Yu S.-J; Lee Y.-C; CHIA-HSIANG YANG Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference
292021A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of MicrorobotsCHIA-HSIANG YANG ; Chung C; CHIA-HSIANG YANG IEEE Journal of Solid-State Circuits
302021Hybrid Precoding Baseband Processor for 64x 64 Millimeter Wave MIMO SystemsCHIA-HSIANG YANG ; Kao C; Chen C; CHIA-HSIANG YANG IEEE Transactions on Circuits and Systems I: Regular Papers
312021A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image DeblurringCHIA-HSIANG YANG ; Chen P.-S; Chen Y.-L; Lee Y.-C; Fu Z.-S; CHIA-HSIANG YANG Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference
322021A color doppler processing engine with an adaptive clutter filter for portable ultrasound imaging devicesCHIA-HSIANG YANG ; Lo Y.-L; CHIA-HSIANG YANG ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
3320214.7 A 91mW 90fps Super-Resolution Processor for Full HD ImagesCHIA-HSIANG YANG ; Shen H.-Y; Lee Y.-C; Tong T.-W; CHIA-HSIANG YANG Digest of Technical Papers - IEEE International Solid-State Circuits Conference
342021Design optimization for ADMM-Based SVM Training Processor for Edge ComputingCHIA-HSIANG YANG ; Huang S.-A; Hsieh Y.-Y; CHIA-HSIANG YANG 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021
352020Pressure-impedance analysis: Assist the diagnosis and classification of ineffective esophageal motility disorderJIA-FENG WU ; I-JUNG TSAI ; Tong, TW; YI-CHENG LIN ; CHIA-HSIANG YANG ; PING-HUEI TSENG JOURNAL OF GASTROENTEROLOGY AND HEPATOLOGY43
362020A 1.9-mW SVM Processor with On-Chip Active Learning for Epileptic Seizure ControlHuang, S.-A.; Chang, K.-C.; HORNG-HUEI LIOU ; CHIA-HSIANG YANG IEEE Journal of Solid-State Circuits3223
372020Improved design and in vivo animal tests of bone-guided cochlear implant microsystem with monopolar biphasic multiple stimulation and neural action potential acquisitionWang S.-H; Huang Y.-K; Chen C.-Y; Lee C.-F; Yang C.-H; Hung C.-C; Liu C.-H; Ker M.-D; CHIEN-HAO LIU ; CHIA-HSIANG YANG 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 202030
382020Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOSCHIA-HSIANG YANG ; Chiueh, H.; Yang, C.-H.; Wen, C.H.-P.; Yang, C.-G.; Chien, P.-H.; Hung, C.-Y.; Chen, Y.-J.; Wang, Y.-P.; Chiu, C.-F.; Lin, J.; CHIA-HSIANG YANG 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
392020Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11axCHIA-HSIANG YANG ; Wang Y.-P; Wen C.-C; Kao C.-C; Huang C.-J; Liu D.-Z; CHIA-HSIANG YANG 2020 IEEE Global Communications Conference, GLOBECOM 2020 - Proceedings
402020Digital Logic and Asynchronous Datapath with Heterogeneous TFET-MOSFET Structure for Ultralow-Energy ElectronicsCHIA-HSIANG YANG ; Hung, J.; Wang, P.; Lo, Y.; Yang, C.; Tsui, B.; CHIA-HSIANG YANG IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
412020A Fully Integrated Genetic Variant Discovery SoC for Next-Generation SequencingCHIA-HSIANG YANG ; Wu, Y.-C.; Chen, Y.-L.; Yang, C.-H.; Lee, C.-H.; Yu, C.-Y.; Chang, N.-S.; Chen, L.-C.; Chang, J.-R.; Lin, C.-P.; Chen, H.-L.; Chen, C.-S.; Hung, J.-H.; CHIA-HSIANG YANG Digest of Technical Papers - IEEE International Solid-State Circuits Conference
422020A 1.5 mW Programmable Acoustic Signal Processor for Hearing Assistive Devices with Speech Intelligibility EnhancementCHIA-HSIANG YANG ; Lin Y.-J; Lee Y.-C; Liu H.-M; Chiueh H; Chi T.-S; CHIA-HSIANG YANG IEEE Transactions on Circuits and Systems I: Regular Papers
432020A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular SystemsCHIA-HSIANG YANG ; Wen, C.-C.; Lee, Y.-C.; Wu, Y.-C.; Kao, C.-C.; CHIA-HSIANG YANG IEEE Symposium on VLSI Circuits, Digest of Technical Papers
442020A 2.17-mw acoustic dsp processor with cnn-fft accelerators for intelligent hearing assistive devicesCHIA-HSIANG YANG ; Lee, Y.-C.; Chi, T.-S.; CHIA-HSIANG YANG IEEE Journal of Solid-State Circuits
452020A 1.5£gJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro RobotsCHIA-HSIANG YANG ; Chung, C.; CHIA-HSIANG YANG Digest of Technical Papers - IEEE International Solid-State Circuits Conference
462019A 2.25 TOPS/W fully-integrated deep CNN learning processor with on-chip trainingLu C.-H; Wu Y.-C; CHIA-HSIANG YANG Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019140
472019A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided DevicesCHIA-HSIANG YANG ; Lee, Y.-C.; Chi, T.-S.; CHIA-HSIANG YANG Proceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019
482019An integrated message-passing detector and decoder for polar-coded massive MU-MIMO systemsCHIA-HSIANG YANG ; Chen, Y.-T.; Sun, W.-C.; Cheng, C.-C.; Tsai, T.-L.; Ueng, Y.-L.; CHIA-HSIANG YANG IEEE Transactions on Circuits and Systems I: Regular Papers
492019A Hardware-Efficient ADMM-Based SVM Training Algorithm for Edge Computing.CHIA-HSIANG YANG ; Huang, Shuo-An; CHIA-HSIANG YANG CoRR
502019Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs.CHIA-HSIANG YANG ; Wang, Yu-Zhe; Wu, Jingjie; Chen, Shi-Hao; Chao, Mango Chia-Tso; CHIA-HSIANG YANG International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, April 22-25, 2019
512019An LDPC-Coded SCMA receiver with multi-user iterative detection and decodingCHIA-HSIANG YANG ; Sun, W.-C.; Su, Y.-C.; Ueng, Y.-L.; CHIA-HSIANG YANG IEEE Transactions on Circuits and Systems I: Regular Papers
522019A 12.6 mW, 573-2901 kS/s Reconfigurable Processor for Reconstruction of Compressively Sensed Physiological SignalsCHIA-HSIANG YANG ; Wang, Y.-Z.; Wang, Y.-P.; Wu, Y.-C.; CHIA-HSIANG YANG IEEE Journal of Solid-State Circuits
532019Iterative Inter-Cell Interference Cancellation Receiver for LDPC-Coded MIMO SystemsCHIA-HSIANG YANG ; Sun, W.-C.; Chen, Y.-T.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG IEEE Transactions on Signal Processing
542018A 12.6mW 573-2,901KS/s Reconfigurable Processor for Reconstruction of Compressively-Sensed Physiological SignalsY.-Z. Wang; Y.-P. Wang; Y.-C. Wu; C.-H. Yang; CHIA-HSIANG YANG Int. Symposium on VLSI Circuits (VLSI Circuits)30
552018A 1.9-mW SVM Processor with On-chip Active Learning for Epileptic Seizure ControlHuang S.-A.; Chang K.-C.; HORNG-HUEI LIOU ; Yang C.-H.; CHIA-HSIANG YANG Int. Symposium on VLSI Circuits (VLSI Circuits)90
562018Performance of pre-production band 1 receiver for the Atacama Large Millimeter/submillimeter Array (ALMA)Huang Y.-D.T; Morata O; Koch P.M; Kemper C; Hwang Y.-J; Chiong C.-C; Ho P.T.P; Chu Y.-H; Huang C.-D; Liu C.-T; Hsieh F.-C; Tseng Y.-H; CHIA-HSIANG YANG ; Tsay J.J; Chang T; Ho C.-T; Chiang P.-H; Chang C.-C; Jian S.-T; Hsu S.-P; Chien C; Iguchi S; Asayama S; Iono D; Gonzalez A; Effland J; Saini K; Pospieszalski M; Henke D; Yeung K; Finger R; Tapia V; Reyes N.Proceedings of SPIE - The International Society for Optical Engineering50
572018Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC)Lin, T.-H.; Yang, C.-H.; TSUNG-HSIEN LIN ; CHIA-HSIANG YANG IEEE Journal of Solid-State Circuits00
582018A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-ChipT.-I Chou; K.-H. Chang; J.-Y. Jhang; S.-W. Chiu; G. Wang; CHIA-HSIANG YANG ; H. Chiueh; H. Chen; C.-C. Hsieh; M.-F. Chang; K.-T. TangIEEE Transactions on Circuits and Systems II54
592018Diagnostic Role of Anal Sphincter Relaxation Integral in High-Resolution Anorectal Manometry for Hirschsprung Disease in InfantsJIA-FENG WU ; CHENG-HSUN LU ; CHIA-HSIANG YANG ; I-JUNG TSAI Journal of Pediatrics2310
602018A 2x2-16x16 Reconfigurable GGMD Processor for MIMO Communication SystemsC.-H. Chiang; S.-A. Huang; C.-E. Chen; C.-H. Yang; CHIA-HSIANG YANG Int. Symposium Circuits and Systems (ISCAS)
612018A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO SystemsC.-Y. Yeh; T.-C. Chu; C.-E. Chen; CHIA-HSIANG YANG IEEE Transactions on Circuits and Systems I: Regular Paper33
622018Massive MIMO detection VLSI design.CHIA-HSIANG YANG 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018
632018A 2กั2-16กั16 Reconfigurable GGMD Processor for MIMO Communication SystemsCHIA-HSIANG YANG ; Chiang, C.-H.; Huang, S.-A.; Chen, C.-E.; CHIA-HSIANG YANG Proceedings - IEEE International Symposium on Circuits and Systems
642018A 12.6MW 573-2,901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological SignalsCHIA-HSIANG YANG ; Wang Y.-Z; Wang Y.-P; Wu Y.-C; CHIA-HSIANG YANG IEEE Symposium on VLSI Circuits, Digest of Technical Papers
652018Distal contractile to impedance integral ratio assist the diagnosis of pediatric ineffective esophageal motility disorderJIA-FENG WU ; Chung, Chieh; PING-HUEI TSENG ; I-JUNG TSAI ; Lin, Yi-Cheng; CHIA-HSIANG YANG ; YI-CHENG LIN Pediatric Research44
662017A 501mW 7.61Gb/s Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MIMO SystemsY.-T. Chen; C.-C. Cheng; T.-L. Tsai; W.-C. Sun; Y.-L. Ueng; C.-H. Yang; CHIA-HSIANG YANG Int. Symposium on VLSI Circuits (VLSI)190
672017A 5.28-Gbps LDPC Decoder with Time-domain Signal Processing for IEEE 802.15.3c ApplicationsM.-R. Li; C.-H. Yang; Y.-L. Ueng; CHIA-HSIANG YANG IEEE Journal of Solid-State Circuits
682017An Area-Efficient Multi-Mode LLR Computing Engine for MMSE-Based MIMO DetectorsW.-C. Sun; C.-H. Yang; Y.-L. Ueng; CHIA-HSIANG YANG IEEE Vehicular Technology Conference10
692017Integration of Energy-Recycling Logic and Wireless Power Transfer for Ultra-Low-Power ImplantablesH.-T. Lin; Y.-C. Wu; P.-H. Hsieh; C.-H. Yang; CHIA-HSIANG YANG Int. Symposium Circuits and Systems (ISCAS)10
702017A 135mW Fully Integrated Data Processor for Next-Generation SequencingY.-C. Wu; J.-H. Hung; C.-H. Yang; CHIA-HSIANG YANG Int. Solid-State Circuits Conference (ISSCC)80
712017A Bone-Guided Cochlear Implant CMOS Microsystem Preserving Acoustic HearingX.-H. Qian; Y.-C. Wu; T.-Y. Yang; C.-H. Cheng; H.-C. Chu; W.-H. Cheng; T.-Y. Yen,T.-H. Lin; Y.-J. Lin; Y.-C. Lee; J.-H. Chang; S.-T. Lin; S.-H. Li; T.-C. Wu; C.-C. Huang; C.-F. Lee; C.-H. Yang; C.-C. Hung; T.-S. Chi; C.-H. Liu; M.-D. Ker; C.-Y. Wu; CHIA-HSIANG YANG Int. Symposium on VLSI Circuits (VLSI)110
722017A Flexible Geometric Mean Decomposition Processor for MIMO Communication SystemsY.-C. Tsai; C.-E. Chen; C.-H. Yang; CHIA-HSIANG YANG IEEE Transaction on Circuits & Systems I (TCAS-I)55
732017Extreme index finder and finding method thereofM.-R. Li; C.-H. Yang; Y.-L. Ueng; CHIA-HSIANG YANG 
742017A 135-mW Fully Integrated Data Processor for Next-Generation SequencingCHIA-HSIANG YANG ; Wu, Y.-C.; Chang, C.-H.; Hung, J.-H.; CHIA-HSIANG YANG IEEE Transactions on Biomedical Circuits and Systems
752017A 5.28-Gb/s LDPC Decoder With Time-Domain Signal Processing for IEEE 802.15.3c ApplicationsCHIA-HSIANG YANG ; Li, M.-R.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG IEEE Journal of Solid-State Circuits
762017A 501mW 7.6lGb/s integrated message-passing detector and decoder for polar-coded massive MIMO systemsCHIA-HSIANG YANG ; Chen Y.-T; Cheng C.-C; Tsai T.-L; Sun W.-C; Ueng Y.-L; CHIA-HSIANG YANG IEEE Symposium on VLSI Circuits, Digest of Technical Papers
772016Multiple Input Multiple Output Wireless Communication System and Channel Decomposition Method ThereofC.-H. Yang; Y.-C. Tsai; CHIA-HSIANG YANG 
782016Multiple Input Multiple Output Wireless Communication System and Channel Decomposition Method ThereofC.-H. Yang; Y.-C. Tsai; CHIA-HSIANG YANG 
792016Sampling Circuit and Master-Slave Flip-FlopS.-J. Jou; C.-H. Yang; W.-C. Liu; C.-W. Lo; C.-D. Chan; CHIA-HSIANG YANG 
802016Data allocating apparatus, signal processing apparatus, and data allocating methodC.-H. Yang; H.-M. Liu; Y.-J. Lin; CHIA-HSIANG YANG 
812016sBWT: Memory Efficient Implementation of the Hardware-acceleration-friendly Schindler Transform for the Fast Biological Sequence MappingC.-H. Chang; M.-T. Chou; Y.-C. Wu; T.-W. Hong; Y.-L. Li; C.-H. Yang; J.-H. Hung; CHIA-HSIANG YANG Bioinformatics87
822016Energy Recycling Systems and Recycling Method ThereofC.-H. Yang; P.-H. Hsieh; C.-Y. Lee; CHIA-HSIANG YANG 
832016Method and system for constrained power allocation in the multi-input multi-output systemsC.-H. Yang; C.-E. Chen; C.-W. Jou; CHIA-HSIANG YANG 
842016Design of a 0.5V 1.68mW Nose-on-a-Chip for Rapid Screen of Chronic Obstructive Pulmonary DiseaseT.-I. Chou; S.-W. Chiu; K.-H. Chang; Y.-J. Chen; C.-T. Tang; C.-H. Shih; C.-C. Hsieh; M.-F. Chang; C.-H. Yang; H. Chiueh; K.-T. Tang; CHIA-HSIANG YANG IEEE Biomedical Circuits & Systems Conf. (BioCAS)00
852016A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy SavingCHIA-HSIANG YANG ; Lee, C.-Y.; Hsieh, P.-H.; CHIA-HSIANG YANG IEEE Transactions on Circuits and Systems I: Regular Papers
862016Error-resilient sequential cells with successive time borrowing for stochastic computingCHIA-HSIANG YANG ; Liu, W.-C.; Chan, C.-D.; Huang, S.-A.; Lo, C.-W.; Yang, C.-H.; Jou, S.-J.; CHIA-HSIANG YANG ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
872016A 98.6μW acoustic signal processor for fully-implantable cochlear implantsCHIA-HSIANG YANG ; Liu, H.-M.; Lin, Y.-J.; Lee, Y.-C.; Lee, C.-Y.; CHIA-HSIANG YANG 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
882015A Concept of Heterogeneous Circuits with Epitaxial Tunnel Layer Tunnel FETsJ.-H. Hung; P.-Y. Wang; B.-Y. Tsui; C.-H. Yang; CHIA-HSIANG YANG Int. Conf. Solid State Devices and Materials (SSDM)00
892015A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated PneumoniaCHIA-HSIANG YANG IEEE Transactions on Biomedical Circuits and Systems
902015An iterative detection and decoding receiver for LDPC-coded MIMO systemsCHIA-HSIANG YANG ; Sun, W.-C.; Wu, W.-H.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG IEEE Transactions on Circuits and Systems I: Regular Papers
912015A 794Mbps 135mW iterative detection and decoding receiver for 4x4 LDPC-coded MIMO systems in 40nmCHIA-HSIANG YANG ; Wu, W.-H.; Sun, W.-C.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG IEEE Symposium on VLSI Circuits
922015A Systolic Array Based GTD Processor With a Parallel AlgorithmCHIA-HSIANG YANG ; Yang, C.-H.; Chou, C.-W.; Hsu, C.-S.; Chen, C.-E.; CHIA-HSIANG YANG IEEE Transactions on Circuits and Systems I: Regular Papers
932015An iterative geometric mean decomposition algorithm for MIMO communications systemsCHIA-HSIANG YANG ; Chen, C.-E.; Tsai, Y.-C.; CHIA-HSIANG YANG IEEE Transactions on Wireless Communications
942014Unequal Bit-reliability Information Storage Method for Communication and Storage SystemsY.-L. Ueng; C.-H. Yang; M. R. Li; CHIA-HSIANG YANG 
952014A fully integrated 8-channel closed-loop neural-prosthetic cmos soc for real-time epileptic seizure controlCHIA-HSIANG YANG et al. IEEE Journal of Solid-State Circuits183162
96201424.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumoniaCHIA-HSIANG YANG IEEE International Solid-State Circuits Conference
972014An 81.6 μW FastICA Processor for Epileptic Seizure DetectionCHIA-HSIANG YANG ; Yang, C.-H.; Shih, Y.-H.; Chiueh, H.; CHIA-HSIANG YANG IEEE Transactions on Biomedical Circuits and Systems
982014A 5.4 μw soft-decision bch decoder for wireless body area networksCHIA-HSIANG YANG ; Yang, C.-H.; Huang, T.-Y.; Li, M.-R.; Ueng, Y.-L.; CHIA-HSIANG YANG IEEE Transactions on Circuits and Systems I: Regular Papers
992014A fully parallel ldpc decoder architecture using probabilistic min-sum algorithm for high-throughput applicationsCHIA-HSIANG YANG ; Cheng, C.-C.; Yang, J.-D.; Lee, H.-C.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG IEEE Transactions on Circuits and Systems I: Regular Papers
1002013A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure controlCHIA-HSIANG YANG IEEE International Solid-State Circuits Conference
1012013Power and area reduction in multi-stage addition using operand segmentationCHIA-HSIANG YANG ; Chan, C.-D.; Liu, W.-C.; Yang, C.-H.; Jou, S.-J.; CHIA-HSIANG YANG 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
1022013A 191μW BPSK demodulator for data and power telemetry in biomedical implantsCHIA-HSIANG YANG ; Wang, L.-L.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG ACM Great Lakes Symposium on VLSI, GLSVLSI
1032013A 28.6μW mixed-signal processor for epileptic seizure detectionCHIA-HSIANG YANG ; Chen, T.-J.; Lee, S.-C.; Yang, C.-H.; Chiu, C.-F.; Chiueh, H.; CHIA-HSIANG YANG IEEE Symposium on VLSI Circuits
1042013A hierarchical approach for online temporal lobe seizure detection in long-term intracranial EEG recordingsCHIA-HSIANG YANG ; Liang, S.-F.; Chen, Y.-C.; Wang, Y.-L.; Chen, P.-T.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG Journal of Neural Engineering
1052012Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection.CHIA-HSIANG YANG ; Shih, Yi-Hsin; Chen, Tsan-Jieh; Yang, Chia-Hsiang; Chiueh, Herming; CHIA-HSIANG YANG Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA 2012, Hollywood, CA, USA, December 3-6, 2012
1062012Power and area minimization of reconfigurable FFT processors: A 3GPP-LTE exampleCHIA-HSIANG YANG ; Yang, C.-H.; Yu, T.-H.; Markovi?, D.; CHIA-HSIANG YANG IEEE Journal of Solid-State Circuits
1072012Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detectionCHIA-HSIANG YANG ; Shih, Y.-H.; Chen, T.-J.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG 2012 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012
1082012A 7.4-mW 200-MS/s wideband spectrum sensing digital baseband processor for cognitive radiosCHIA-HSIANG YANG ; Yu, T.-H.; Yang, C.-H.; Čabrić, D.; Marković, D.; CHIA-HSIANG YANG IEEE Journal of Solid-State Circuits
1092011A 75μW, 16-channel neural spike-sorting processor with unsupervised clusteringKarkare, Vaibhav; Gibson, Sarah; CHIA-HSIANG YANG ; Chen, Henry; Marković, DejanIEEE Symposium on VLSI Circuits
1102011An energy-efficient VLSI architecture for cognitive radio wideband spectrum sensingCHIA-HSIANG YANG ; Yu, T.-H.; Yang, C.-H.; Marković, D.; Čabrić, D.; CHIA-HSIANG YANG GLOBECOM - IEEE Global Telecommunications Conference
1112011A hardware-efficient VLSI architecture for hybrid sphere-MCMC detectionCHIA-HSIANG YANG ; Yuan, F.-L.; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG GLOBECOM - IEEE Global Telecommunications Conference
1122011A 7.4mW 200MS/s wideband spectrum sensing digital baseband processor for cognitive radiosCHIA-HSIANG YANG ; Yu, T.-H.; Yang, C.-H.; Čabrić, D.; Marković, D.; CHIA-HSIANG YANG IEEE Symposium on VLSI Circuits
1132010AMiBA wideband analog correlatorLi, C.-T.; TZI-DAR CHIUEH ; JIUN-HUEI PROTY WU ; CHIA-HSIANG YANG et al. Astrophysical Journal1617
1142010A 5.8mW 3GPP-LTE compliant 8×8 MIMO sphere decoder chip with soft-outputsCHIA-HSIANG YANG ; Yang, C.-H.; Yu, T.-H.; Marković, D.; CHIA-HSIANG YANG IEEE Symposium on VLSI Circuits
1152009The yuan-tseh lee array for microwave background anisotropyHo, P.T.P.; Altamirano, P.; Chang, C.-H.; Chang, S.-H.; Chang, S.-W.; Chen, C.-C.; Chen, K.-J.; Chen, M.-T.; Han, C.-C.; Ho, W.M.; Huang, Y.-D.; Hwang, Y.-J.; Ib?ez-Romano, F.; Jiang, H.; Koch, P.M.; Kubo, D.Y.; Li, C.-T.; Lim, J.; Lin, K.-Y.; Liu, G.-C.; Lo, K.-Y.; Ma, C.-J.; Martin, R.N.; Martin-Cocher, P.; Molnar, S.M.; Ng, K.-W.; Nishioka, H.; O'Connell, K.E.; Oshiro, P.; Patt, F.; Raffin, P.; Umetsu, K.; Wei, T.; Wu, J.-H.P.; Chiueh, T.-D.; Chiueh, T.; Chu, T.-H.; Huang, C.-W.L.; Hwang, W.Y.P.; Liao, Y.-W.; Lien, C.-H.; Wang, F.-C.; Wang, H.; Wei, R.-M.; Yang, C.-H.; Kesteven, M.; Kingsley, J.; Sinclair, M.M.; Wilson, W.; Birkinshaw, M.; Liang, H.; Lancaster, K.; Park, C.-G.; Pen, U.-L.; TZI-HONG CHIUEH ; W-Y HWANG ; CHIA-HSIANG YANG ; Chang, Chia-Hao; TAH HSIUNG CHU ; FU-CHENG WANG ; HUEI WANG ; TZI-DAR CHIUEH ; JIUN-HUEI PROTY WU Astrophysical Journal3840
1162009A 2.89mW 50GOPS 16 × 16 16-core MIMO sphere decoder in 90nm CMOSCHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG ESSCIRC 2009 - 35th European Solid-State Circuits Conference
1172009A flexible DSP architecture for MIMO sphere decodingCHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG IEEE Transactions on Circuits and Systems I: Regular Papers
1182008A flexible VLSI architecture for extracting diversity and spatial multiplexing gains in MIMO channelsCHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG IEEE International Conference on Communications
1192008DSP architecture optimization in Matlab/Simulink environmentCHIA-HSIANG YANG ; N; a, R.; Yang, C.-H.; Markovic, D.; CHIA-HSIANG YANG IEEE Symposium on VLSI Circuits
1202008A multi-core sphere decoder VLSI architecture for MIMO communicationsCHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG GLOBECOM - IEEE Global Telecommunications Conference
1212005A 1.2V 6.7mW impulse-radio UWB baseband transceiverCHIA-HSIANG YANG ; Yang, C.-H.; Chen, K.-H.; Chiueh, T.-D.; CHIA-HSIANG YANG IEEE International Solid-State Circuits Conference
1222004Design of a low-complexity receiver for impulse-radio ultra-wideband communication systemsYang, Chia-Hsiang ; Lin, Yu-Hsuan; Lin, Shih-Chun; Chiueh, Tzi-Dar 2004 International Symposium on Circuits and Systems, 2004. ISCAS '0470
1232004A wideband analog correlator system for AMiBALi, C.-T.; Kubo, D.; Han, C.-C.; Chen, C.-C.; Chen, M.-T.; Lien, C.-H.; Wang, H.; Wei, R.-M.; Yang, C.-H.; Chiueh, T.-D.; Peterson, J.; Kesteven, M.; TZI-DAR CHIUEH ; CHIA-HSIANG YANG ; HUEI WANG Proceedings of SPIE - The International Society for Optical Engineering180