第 1 到 235 筆結果,共 235 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2019 | Many-body theory of optical absorption in doped two-dimensional semiconductors | Chang, Y.-W.; Reichman, D.R.; YAO-WEN CHANG | Physical Review B | 25 | 23 | |
2 | 2019 | Graph-and ILP-based cut redistribution for two-dimensional directed self-assembly | Wang, Z.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 1 | 0 | |
3 | 2019 | DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography | Su, Y.-H.; Chang, Y.-W. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
4 | 2019 | Obstacle-aware group-based length-matching routing for pre-assignment area-I/O flip-chip designs | Chang, Y.-H.; Wen, H.-T.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 3 | 0 | |
5 | 2019 | BiG: A bivariate gradient-based wirelength model for analytical circuit placement | Sunl, F.-K.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 5 | 0 | |
6 | 2019 | Analytical Mixed-cell-height legalization considering average and maximum movement minimization | Li, X.; Chen, J.; Zhu, W.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings of the International Symposium on Physical Design | 14 | 0 | |
7 | 2019 | A DAG-based algorithm for obstacle-aware topology-matching on-track bus routing | Hsu, C.-H.; Hungz, S.-C.; Chenz, H.; Sunz, F.-K.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 1 | 0 | |
8 | 2019 | MDP-trees: Multi-Domain Macro Placement for Ultra Large-Scale Mixed-Size Designs | Y. C. Liu; T. C. Chen; Y. W. Chang; S. Y. Kuo; Chang, Y.-W. | 24th Asia and South Pacific Design Automation Conference (ASP-DAC 2019) | 4 | 0 | |
9 | 2018 | NTU place4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs with Technology and Region Constraints | Huang, C.-C.; Lee, H.-Y.; Lin, B.-Q.; Yang, S.-W.; Chang, C.-H.; Chen, S.-T.; Chang, Y.-W. ; Chen, T.-C.; Bustany, I. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 34 | 31 | |
10 | 2018 | Generalized augmented lagrangian and its applications to VLSI global placement | Zhu, Z.; Chen, J.; Peng, Z.; Zhu, W.; Chang, Y.-W. | Design Automation Conference | 15 | 0 | |
11 | 2018 | Mixed-cell-height placement with complex minimum-implant-area constraints | Chen, J.; Yang, P.; Li, X.; Zhu, W.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 15 | 0 | |
12 | 2018 | WB-trees: A meshed tree representation for FinFET analog layout designs | Lu, Y.-S.; Chang, Y.-H.; Chang, Y.-W. | Design Automation Conference | 8 | 0 | |
13 | 2018 | Polarized excitons and optical activity in single-wall carbon nanotubes | Chang, Y.-W. ; Jin, B.-Y. | Physical Review B | 1 | 1 | |
14 | 2018 | Provably good max–min-m-neighbor-TSP-based subfield scheduling for electron-beam photomask fabrication | Lin Z.-W; Fang S.-Y; Chang Y.-W; Rao W.-C; CHIEH-HSIUNG KUAN ; Chang, Y.-W. | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2 | 2 | |
15 | 2018 | DSA-Friendly detailed routing considering double patterning and DSA template assignments | Yu, H.-J.; Chang, Y.-W. | Design Automation Conference | 6 | 0 | |
16 | 2018 | Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction | Wang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W. ; Li, J.C.M.; Jiang, J.-H.R.; JIE-HONG JIANG ; CHIEN-MO LI | Design Automation Conference | 5 | 0 | |
17 | 2018 | Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems | Chen, S.-C.; Sun, R.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 16 | 0 | |
18 | 2018 | A multithreaded initial detailed routing algorithm considering global routing guides | Sun, F.-K.; Chen, H.; Chen, C.-Y.; Hsu, C.-H.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 23 | 0 | |
19 | 2018 | Mixed-cell-height placement considering drain-to-drain abutment | Tseng, Y.-W.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 11 | 0 | |
20 | 2018 | Mixed-cell-height legalization considering technology and region constraints | Zhu, Z.; Li, X.; Chen, Y.; Chen, J.; Zhu, W.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 14 | 0 | |
21 | 2018 | Analytical solution of Poisson's equation and its application to VLSI global placement | Zhu, W.; Huang, Z.; Chen, J.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 13 | 0 | |
22 | 2017 | FPGA placement and routing | Chen, S.-C.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 16 | 0 | |
23 | 2017 | Nanowire-Aware Routing Considering High Cut Mask Complexity | Su, Y.-H.; Chang, Y.-W. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 0 | |
24 | 2017 | Generalized force directed relaxation with optimal regions and its applications to circuit placement | Chang, Y.-W. | International Symposium on Physical Design | 1 | 0 | |
25 | 2017 | An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs | Chen, S.-T.; Chang, Y.-W. ; Chen, T.-C. | IEEE/ACM International Conference on Computer-Aided Design | 4 | 0 | |
26 | 2017 | Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs | Chen, J.; Zhu, Z.; Zhu, W.; Chang, Y.-W. | Design Automation Conference | 38 | 0 | |
27 | 2017 | Graph-Based Logic Bit Slicing for Datapath-Aware Placement | Huang, C.-C.; Lin, B.-Q.; Lee, H.-Y.; Chang, Y.-W. ; Wu, K.-S.; Yang, J.-Z. | Design Automation Conference | 7 | 0 | |
28 | 2017 | Fogging Effect Aware Placement in Electron Beam Lithography | Huang, Y.-C.; Chang, Y.-W. | Design Automation Conference | 7 | 0 | |
29 | 2017 | Redistribution layer routing for wafer-level integrated fan-out package-on-packages | Lin, T.-C.; Chi, C.-C.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 9 | 0 | |
30 | 2017 | A novel damped-wave framework for macro placement | Chang, C.-H.; Chang, Y.-W. ; Chen, T.-C. | IEEE/ACM International Conference on Computer-Aided Design | 12 | 0 | |
31 | 2017 | Mixed-cell-height detailed placement considering complex minimum-implant-area constraints | Wu, Y.-Y.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 17 | 0 | |
32 | 2017 | Cut Redistribution with Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts | Lin, Z.-W.; Chang, Y.-W. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
33 | 2017 | Blockage-aware terminal propagation for placement wirelength minimization | Yang, S.-W.; Chang, Y.-W. ; Chen, T.-C. | IEEE/ACM International Conference on Computer-Aided Design | 0 | 0 | |
34 | 2017 | Clock-aware placement for large-scale heterogeneous FPGAs | Kuo, Y.-C.; Huang, C.-C.; Chen, S.-C.; Chiang, C.-H.; Chang, Y.-W. ; Kuo, S.-Y. | IEEE/ACM International Conference on Computer-Aided Design | 12 | 0 | |
35 | 2017 | Theory of charge transport in molecular junctions: Role of electron correlation | Chang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG | Journal of Chemical Physics | 2 | 2 | |
36 | 2017 | An effective legalization algorithm for mixed-cell-height standard cells | Wang, C.-H.; Wu, Y.-Y.; Chen, J.; Chang, Y.-W.; Kuo, S.-Y.; Zhu, W.; SY-YEN KUO ; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 40 | 0 | |
37 | 2017 | Detailed Placement for Two-Dimensional Directed Self-Assembly Technology | Lin, Z.-W.; Chang, Y.-W. | Design Automation Conference | 3 | 0 | |
38 | 2016 | Fast lithographic mask optimization considering process variation | Su, Y.-H.; Huang, Y.-C.; Tsai, L.-C.; Chang, Y.-W.; Banerjee, S.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 34 | 30 | |
39 | 2016 | Cut redistribution with directed self-assembly templates for advanced 1-D gridded layouts | Lin, Z.-W.; Chang, Y.-W. | Asia and South Pacific Design Automation Conference, ASP-DAC | 16 | 0 | |
40 | 2016 | Provably good max-min-m-neighbor-TSP-based subfield scheduling for electron-beam photomask fabrication | Lin, Z.-W.; Fang, S.-Y.; Chang, Y.-W. ; Rao, W.-C.; CHIEH-HSIUNG KUAN ; YAO-WEN CHANG | 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 | 1 | 0 | |
41 | 2016 | DSA-compliant routing for two-dimensional patterns using block copolymer lithography | Su, Y.-H.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 4 | 0 | |
42 | 2016 | Layout-Dependent Effects-Aware Analytical Analog Placement | Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 44 | 37 | |
43 | 2016 | Simultaneous EUV flare variation minimization and CMP control by coupling-aware dummification | Chiang, H.-J.K.; Liu, C.-Y.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG ; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 5 | 4 | |
44 | 2016 | Minimum-implant-area-aware detailed placement with spacing constraints | Tseng, K.-H.; Chang, Y.-W.; Liu, C.C.C.; YAO-WEN CHANG | Design Automation Conference | 18 | 0 | |
45 | 2016 | Recent research development and new challenges in analog layout synthesis | Lin, M.P.-H.; Chang, Y.-W.; Hung, C.-M.; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 43 | 0 | |
46 | 2016 | Circular-contour-based obstacle-aware macro placement | Chiou, C.-H.; Chang, C.-H.; Chen, S.-T.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 14 | 0 | |
47 | 2016 | Double-patterning aware DSA template guided cut redistribution for advanced 1-D gridded designs | Lin, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 18 | 0 | |
48 | 2016 | VCR: Simultaneous via-template and cut-template-aware routing for directed self-assembly technology | Su, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 4 | 0 | |
49 | 2016 | Detailed-routability-driven analytical placement for mixed-size designs with technology and region constraints | Huang, C.-C.; Lee, H.-Y.; Lin, B.-Q.; Yang, S.-W.; Chang, C.-H.; Chen, S.-T.; Chang, Y.-W.; YAO-WEN CHANG | 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 | 17 | 0 | |
50 | 2016 | Redistribution layer routing for integrated fan-out wafer-level chip-scale packages | Lin, B.-Q.; Lin, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 12 | 0 | |
51 | 2016 | QB-trees: Towards an optimal topological representation and its applications to analog layout designs | Wu, I.-P.; Ou, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 12 | 0 | |
52 | 2015 | Layout-dependent-effects-aware analytical analog placement | Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 15 | 0 | |
53 | 2015 | Fast lithographic mask optimization considering process variation | Su, Y.-H.; Huang, Y.-C.; Tsai, L.-C.; Chang, Y.-W.; Banerjee, S.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 9 | 0 | |
54 | 2015 | Non-stitch triple patterning-aware routing based on conflict graph pre-coloring | Hsu, P.-Y.; Chang, Y.-W.; YAO-WEN CHANG | 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 | 8 | 0 | |
55 | 2015 | Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning | Fang, S.-Y.; Tai, Y.-S.; Chang, Y.-W.; YAO-WEN CHANG | 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 | 7 | 0 | |
56 | 2015 | Routing-architecture-aware analytical placement for heterogeneous FPGAS | Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 18 | 0 | |
57 | 2015 | Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAS | Chen, Y.-C.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 27 | 0 | |
58 | 2015 | Nanowire-aware routing considering high cut mask complexity | Su, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 11 | 0 | |
59 | 2015 | Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits | Ho, K.-H.; Ou, H.-C.; Chang, Y.-W.; Tsao, H.-F.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 12 | 11 | |
60 | 2015 | Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography | Ou, H.-C.; Tseng, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 2 | 0 | |
61 | 2015 | EUV and e-beam manufacturability: Challenges and solutions | Chang, Y.-W.; Liu, R.-G.; Fang, S.-Y.; YAO-WEN CHANG | Design Automation Conference | 15 | 0 | |
62 | 2015 | Stitch-aware routing for multiple e-beam lithography | Liu, I.-J.; Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 6 | 6 | |
63 | 2015 | Detailed-Routing-Driven analytical standard-cell placement | Huang, C.-C.; Chiou, C.-H.; Tseng, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 | 18 | 0 | |
64 | 2014 | Buffered clock tree synthesis considering self-heating effects | Lin, C.-W.; Hsu, T.-H.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Low Power Electronics and Design | 1 | 0 | |
65 | 2014 | Overlay-Aware detailed routing for self-Aligned double patterning lithography using the cut process | Liu, I.-J.; Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 25 | 0 | |
66 | 2014 | Obstacle-avoiding free-assignment routing for flip-chip designs | Ho, Y.-K.; Lee, H.-C.; Lee, W.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 9 | 9 | |
67 | 2014 | A new asynchronous pipeline template for power and performance optimization | Ho, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 8 | 0 | |
68 | 2014 | Simultaneous EUV flare- and CMP-aware placement | Liu, C.-Y.; Chang, Y.-W.; YAO-WEN CHANG | 2014 32nd IEEE International Conference on Computer Design, ICCD 2014 | 5 | 0 | |
69 | 2014 | Nonuniform multilevel analog routing with matching constraints | Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 22 | 18 | |
70 | 2014 | Theory of charge transport in molecular junctions: From Coulomb blockade to coherent tunneling | Chang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG | Journal of Chemical Physics | 4 | 4 | |
71 | 2014 | A novel layout decomposition algorithm for triple patterning lithography | Fang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 46 | 43 | |
72 | 2014 | NTUplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designs | Hsu, M.-K.; Chen, Y.-F.; Huang, C.-C.; Chou, S.; Lin, T.-H.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 53 | 51 | |
73 | 2013 | Multiple chip planning for chip-interposer codesign | Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 28 | 0 | |
74 | 2013 | Graph-based subfield scheduling for electron-beam photomask fabrication | Fang, S.-Y.; Chen, W.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | 7 | |
75 | 2013 | Layer minimization in escape routing for staggered-pin-array PCBs | Ho, Y.-K.; Shih, X.-W.; Chang, Y.-W.; Cheng, C.-K.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 5 | 0 | |
76 | 2013 | An efficient and effective analytical placer for FPGAs | Lin, T.-H.; Banerjee, P.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 36 | 0 | |
77 | 2013 | Escape routing for staggered-pin-array PCBs | Ho, Y.-K.; Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 12 | 11 | |
78 | 2013 | Symmetrical buffered clock-tree synthesis with supply-voltage alignment | Shih, X.-W.; Hsu, T.-H.; Lee, H.-C.; Chang, Y.-W.; Chao, K.-Y.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 4 | 0 | |
79 | 2013 | Simultaneous analog placement and routing with current flow and current density considerations | Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 28 | 0 | |
80 | 2013 | Stitch-aware routing for multiple e-beam lithography | Fang, S.-Y.; Liu, I.-J.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 9 | 0 | |
81 | 2013 | TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average wirelength model | Hsu, M.-K.; Balabanov, V.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 68 | 54 | |
82 | 2013 | Numerical and experimental investigation of polycarbonate vacuum-forming process | Chang, Y.-W.; JUNG-HO CHENG ; YAO-WEN CHANG | Journal of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an | 6 | 6 | |
83 | 2013 | Routability-driven placement for hierarchical mixed-size circuit designs | Hsu, M.-K.; Chen, Y.-F.; Huang, C.-C.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 27 | 0 | |
84 | 2013 | Double patterning lithography-aware analog placement | Chien, H.-C.C.; Ou, H.-C.; Chen, T.-C.; Kuan, T.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 8 | 0 | |
85 | 2012 | Native-conflict and stitch-aware wire perturbation for double patterning technology | Fang, S.-Y.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 20 | 16 | |
86 | 2012 | Non-uniform multilevel analog routing with matching constraints | Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 24 | 0 | |
87 | 2012 | Graph-based subfield scheduling for electron-beam photomask fabrication | Fang, S.-Y.; Chen, W.-Y.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 3 | 0 | |
88 | 2012 | A chip-package-board co-design methodology | Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 4 | 0 | |
89 | 2012 | Statistical thermal modeling and optimization considering leakage power variations | Juan, D.-C.; Chuang, Y.-L.; Marculescu, D.; Chang, Y.-W.; YAO-WEN CHANG | Design, Automation and Test in Europe, DATE | 10 | ||
90 | 2012 | Fast timing-model independent buffered clock-tree synthesis | Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 14 | 10 | |
91 | 2012 | TRECO: Dynamic technology remapping for timing engineering change orders | Ho, K.-H.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG ; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | 8 | |
92 | 2012 | Unified analytical global placement for large-scale mixed-size circuit designs | Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 19 | |
93 | 2012 | Self-interaction correction to GW approximation | Chang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG | Physica Scripta | 4 | 4 | |
94 | 2012 | Obstacle-avoiding free-assignment routing for flip-chip designs | Lee, P.-W.; Lee, H.-C.; Ho, Y.-K.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG | Design Automation Conference | 2 | 0 | |
95 | 2012 | Simultaneous flare level and flare variation minimization with dummification in EUVL | Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 14 | 0 | |
96 | 2012 | Structure-aware placement for datapath-intensive circuit designs | Chou, S.; Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 31 | 0 | |
97 | 2012 | A novel layout decomposition algorithm for triple patterning lithography | Fang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG | Design Automation Conference | 47 | 0 | |
98 | 2012 | Correlation effects of πelectrons on the band structures of conjugated polymers using the self-consistent GW approximation with vertex corrections | Chang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG | Journal of Chemical Physics | 7 | 7 | |
99 | 2011 | Heterogeneous B*-trees for analog placement with symmetry and regularity considerations | Chou, P.-Y.; Ou, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 26 | 0 | |
100 | 2011 | Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips | Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 45 | 33 | |
101 | 2011 | An EOS-Free PNP-enhanced cascoded NMOSFET structure for high voltage application | Wang, S.-Y.; Chang, Y.-W.; Chen, Y.-Y.; He, C.-W.; Wu, G.-W.; Lu, T.-C.; Chen, K.-C.; Lu, C.-Y.; YAO-WEN CHANG | IEEE International Reliability Physics Symposium | 2 | 0 | |
102 | 2011 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Guest Editorial | Saxena, P.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
103 | 2011 | PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs | Chuang, Y.-L.; Lin, H.-T.; Ho, T.-Y.; Chang, Y.-W.; Marculescu, D.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 7 | 0 | |
104 | 2011 | A corner stitching compliant B-tree representation and its applications to analog placement | Tsao, H.-F.; Chou, P.-Y.; Huang, S.-L.; Chang, Y.-W.; Lin, M.P.-H.; Chen, D.-P.; Liu, D.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 23 | 0 | |
105 | 2011 | Escape routing for staggered-pin-array PCBs | Ho, Y.-K.; Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 11 | 0 | |
106 | 2011 | Hierarchical placement with layout constraints | Lin, M.P.-H.; Chang, Y.-W.; YAO-WEN CHANG | Analog Layout Synthesis: A Survey of Topological Approaches | 3 | 0 | |
107 | 2011 | Thermal-driven analog placement considering device matching | Lin, M.P.-H.; Zhang, H.; Wong, M.D.F.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 26 | 20 | |
108 | 2011 | Proceedings of the International Symposium on Physical Design: Foreword | Chang, Y.-W.; Hu, J.; YAO-WEN CHANG | International Symposium on Physical Design | 0 | ||
109 | 2011 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs | Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 3 | |
110 | 2011 | Pulsed-latch aware placement for timing-integrity optimization | Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 3 | 1 | |
111 | 2011 | Routability-driven analytical placement for mixed-size circuit designs | Hsu, M.-K.; Chou, S.; Lin, T.-H.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 63 | 0 | |
112 | 2011 | Simultaneous functional and timing ECO | Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 17 | ||
113 | 2011 | TSV-aware analytical placement for 3D IC designs | Hsu, M.-K.; Chang, Y.-W.; Balabanov, V.; YAO-WEN CHANG | Design Automation Conference | 77 | ||
114 | 2011 | Simultaneous layout migration and decomposition for double patterning technology | Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 17 | |
115 | 2010 | Predictive formulae for OPC with applications to lithography-friendly routing | Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | 9 | |
116 | 2010 | High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees | Shiht, X.-W.; Leet, H.-C.; Hot, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 23 | 0 | |
117 | 2010 | Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis | Falkenstern, P.; Xie, Y.; Chang, Y.-W.; Wang, Y.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 55 | 0 | |
118 | 2010 | ILP-based pin-count aware design methodology for microfluidic biochips | Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 27 | 22 | |
119 | 2010 | Design-hierarchy aware mixed-size placement for routability optimization | Chuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 26 | 0 | |
120 | 2010 | Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips | Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 25 | 0 | |
121 | 2010 | Density gradient minimization with coupling-constrained dummy fill for CMP control | Chen, H.-Y.; Chou, S.-J.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 20 | 0 | |
122 | 2010 | Pulsed-latch aware placement for timing-integrity optimization | Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 20 | 0 | |
123 | 2010 | Area-I/O flip-chip routing for chip-package co-design considering signal skews | Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 23 | 21 | |
124 | 2010 | Unified analytical global placement for large-scale mixed-size circuit designs | Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 8 | 0 | |
125 | 2010 | Template-mask design methodology for double patterning technology | Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 2 | 0 | |
126 | 2010 | Native-conflict-aware wire perturbation for double patterning technology | Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 23 | 0 | |
127 | 2010 | Multilayer global routing with via and wire capacity considerations | Hsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 17 | 16 | |
128 | 2010 | Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization | Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 24 | 0 | |
129 | 2010 | Fast timing-model independent buffered clock-tree synthesis | Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 23 | 0 | |
130 | 2010 | Compositional dependence of phase formation mechanisms at the interface between titanium and calcia-stabilized zirconia at 1550°C | Chang, Y.-W.; Lin, C.-C.; YAO-WEN CHANG | Journal of the American Ceramic Society | 29 | 23 | |
131 | 2010 | Redundant-wires-aware ECO timing and mask cost optimization | Fang, S.-Y.; Chien, T.-F.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 15 | 0 | |
132 | 2010 | ECO timing optimization using spare cells and technology remapping | Ho, K.-H.; Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 15 | |
133 | 2009 | High-performance global routing with fast overflow reduction | Qien, H.-Y.; Hsu, C.-H.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 62 | 0 | |
134 | 2009 | Voltage-Island partitioning and floorplanning under timing constraints | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 11 | |
135 | 2009 | Global and Detailed Routing | Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Electronic Design Automation | 24 | 0 | |
136 | 2009 | Floorplanning | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | Electronic Design Automation | 5 | 0 | |
137 | 2009 | A progressive-ILP-based routing algorithm for the synthesis of cross-referencing biochips | Yuh, P.-H.; Sapatnekar, S.S.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG ; CHIA-LIN YANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2 | 5 | |
138 | 2009 | BIST design optimization for large-scale embedded memory cores | Chien, T.-F.; Chao, W.-C.; Li, C.-M.; Chang, Y.-W.; Liao, K.-Y.; Chang, M.-T.; Tsai, M.-H.; Tseng, C.-M.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 7 | ||
139 | 2009 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs | Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 4 | ||
140 | 2009 | Voltage-island partitioning and floorplanning under timing constraints | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 14 | 11 | |
141 | 2009 | Routing for manufacturability and reliability | Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Circuits and Systems Magazine | 8 | 8 | |
142 | 2009 | Introduction | Stroud, C.E.; Wang, L.T.; Chang, Y.-W.; YAO-WEN CHANG | Electronic Design Automation | 2 | 0 | |
143 | 2009 | Thermal-driven analog placement considering device matching | Lin, P.-H.; Zhang, H.; Wong, M.D.F.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 26 | ||
144 | 2009 | T-trees: A tree-based representation for temporal and three-dimensional floorplanning | Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG ; CHIA-LIN YANG | ACM Transactions on Design Automation of Electronic Systems | 6 | 3 | |
145 | 2009 | Analog layout synthesis - Recent advances in topological approaches | Graeb, H.; Balasa, F.; Castro-Lopez, R.; Chang, Y.-W.; Fern; ez, F.V.; Lin, P.-H.; Strasser, M.; YAO-WEN CHANG | Design, Automation and Test in Europe, DATE | 34 | ||
146 | 2009 | A novel hot-electron programming method in a buried diffusion bit-line SONOS memory by utilizing nonequilibrium charge transport | Wang, T.; Tang, C.-J.; Li, C.-W.; Lee, C.-H.; Ou, T.-F.; Chang, Y.-W.; Tsai, W.-J.; Lu, T.-C.; Chen, K.-C.; Lu, C.-Y.; YAO-WEN CHANG | IEEE Electron Device Letters | 0 | 0 | |
147 | 2009 | Essential issues in analytical placement algorithms | Chang, Y.-W.; Jiang, Z.-W.; Chen, T.-C.; YAO-WEN CHANG | IPSJ Transactions on System LSI Design Methodology | 34 | 0 | |
148 | 2009 | Simultaneous layout migration and decomposition for double patterning technology | Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 26 | ||
149 | 2009 | Electronic Design Automation | Wang, L.-T.; Chang, Y.-W.; Cheng, K.-T.; YAO-WEN CHANG | Electronic Design Automation | 128 | 0 | |
150 | 2009 | Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs | Lee, W.-P.; Marculescu, D.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 10 | 0 | |
151 | 2009 | An efficient pre-assignment routing algorithm for flip-chip designs | Lee, P.-W.; Lin, C.-W.; Chang, Y.-W.; Shen, C.-F.; Tseng, W.-C.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 15 | ||
152 | 2008 | Full-chip routing considering double-via insertion | Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 61 | 46 | |
153 | 2008 | An optimal network-flow-based simultaneous diode and jumper insertion algorithm for antenna fixing | Jiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | 5 | |
154 | 2008 | MP-trees: A packing-based macro placement algorithm for modern mixed-size designs | Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, T.-Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 30 | 27 | |
155 | 2008 | Sensitivity-based multiple-Vt cell swapping for leakage power reduction | Lee, W.-P.; Liu, H.-Y.; Ho, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT | 1 | 0 | |
156 | 2008 | Multilayer obstacle-avoiding rectilinear steiner tree construction based on spanning graphs | Lin, C.-W.; Huang, S.-L.; Hsu, K.-C.; Lee, M.-X.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 18 | 21 | |
157 | 2008 | Effective wire models for X-architecture placement | Chen, T.-C.; Chuang, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 1 | |
158 | 2008 | Constraint graph-based macro placement for modern mixed-size circuit designs | Chen, H.-C.; Chuang, Y.-L.; Chang, Y.-W.; Chang, Y.-C.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 26 | 0 | |
159 | 2008 | Metal-density-driven placement for CMP variation and routability | Chen, T.-C.; Cho, M.; Pan, D.Z.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | 13 | |
160 | 2008 | Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs | Jiang, Z.-W.; Su, B.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 37 | 0 | |
161 | 2008 | Predictive formulae for OPC with applications to lithography-friendly routing | Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 20 | 0 | |
162 | 2008 | Routing for chip-package-board co-design considering differential pairs | Fang, J.-W.; Ho, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 22 | 0 | |
163 | 2008 | Effect of yttria on interfacial reactions between titanium melt and hot-pressed yttria/zirconia composites at 1700°c | Lin, C.-C.; Chang, Y.-W.; Lin, K.-L.; YAO-WEN CHANG | Journal of the American Ceramic Society | 24 | 16 | |
164 | 2008 | Area-I/O flip-chip routing for chip-package co-design | Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 45 | 0 | |
165 | 2008 | Metal-density driven placement for CMP variation and routability | Chen, T.-C.; Cho, M.; Pan, D.Z.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 6 | 0 | |
166 | 2008 | A new multilevel framework for large-scale interconnect-driven floorplanning | Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 28 | 25 | |
167 | 2007 | Thermal-driven interconnect optimization by simultaneous gate and wire sizing | Lin, Y.-W.; Chang, Y.-W.; YAO-WEN CHANG | 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 | 0 | 0 | |
168 | 2007 | A network-flow-based RDL routing algorithmz for flip-chip design | Fang, J.-W.; Lin, I.-J.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 59 | 44 | |
169 | 2007 | MB*-tree: A multilevel floorplanner for large-scale building-module design | Lee, H.-C.; Chang, Y.-W.; Yang, H.H.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 2 | |
170 | 2007 | MP-trees: A packing-based macro placement algorithm for mixed-size designs | Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, D.; YAO-WEN CHANG | Design Automation Conference | 14 | 0 | |
171 | 2007 | X-architecture placement based on effective wire models | Chen, T.-C.; Chuang, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 1 | 0 | |
172 | 2007 | An efficient algorithm for statistical circuit optimization using Lagrangian relaxation | Lin, I.-J.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 2 | 0 | |
173 | 2007 | ECO timing optimization using spare cells | Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 43 | 0 | |
174 | 2007 | X-route: An x-architecture full-chip multilevel router | Chang, C.-F.; Chang, Y.-W.; YAO-WEN CHANG | 20th Anniversary IEEE International SOC Conference | 4 | 0 | |
175 | 2007 | Multilevel full-chip routing with testability and yield enhancement | Li, K.S.-M.; Chang, Y.-W.; Lee, C.-L.; Su, C.; Chen, J.E.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 10 | 5 | |
176 | 2007 | 3D video applications and intelligent video surveillance camera and its VLSI design | Chien, S.-Y.; Shih, C.-S.; Ku, M.-K.; Yang, C.-L.; Chang, Y.-W.; Kuo, T.-W.; Chen, L.-G.; YAO-WEN CHANG | 2007 IEEE International Conference on Multimedia and Expo, ICME 2007 | 0 | ||
177 | 2007 | Challenges and solutions in modern VLSI placement | Jiang, Z.-W.; Chen, H.-.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | 2007 International Symposium on VLSI Design, Automation and Test | 6 | 0 | |
178 | 2007 | Multilevel full-chip gridless routing with applications to optical-proximity correction | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 13 | |
179 | 2007 | Power/ground network and floorplan cosynthesis for fast design convergence | Liu, C.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 13 | |
180 | 2007 | An integer linear programming based routing algorithm for flip-chip design | Fang, J.-W.; Hsu, C.-H.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 51 | 0 | |
181 | 2007 | A statistical approach to the timing-yield optimization of pipeline circuits | Hsu, C.-H.; Chou, S.-J.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG | Lecture Notes in Computer Science | 0 | ||
182 | 2007 | Statistical circuit optimization considering device andinterconnect process variations | Lin, I.-J.; Ling, T.-Y.; Chang, Y.-W.; YAO-WEN CHANG | International Workshop on System Level Interconnect Prediction, SLIP | 4 | 0 | |
183 | 2006 | Current path analysis for electrostatic discharge protection | Liu, H.-Y.; Lin, C.-W.; Chou, S.-J.; Tu, W.-T.; Liu, C.-H.; Chang, Y.-W.; YAO-WEN CHANG ; SY-YEN KUO ; CHUNG-WEI LIN ; CHIH-HUNG LIU | IEEE/ACM International Conference on Computer-Aided Design | 8 | 0 | |
184 | 2006 | An optimal simultaneous diode/jumper insertion algorithm for antenna fixing | Jiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 4 | 0 | |
185 | 2006 | Charge-based capacitance measurement for bias-dependent capacitance | Chang, Y.-W.; Chang, H.-W.; Lu, T.-C.; King, Y.-C.; Ting, W.; Ku, Y.-H.J.; Lu, C.-Y.; YAO-WEN CHANG | IEEE Electron Device Letters | 44 | 36 | |
186 | 2006 | A novel framework for multilevel full-chip gridless routing | Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 14 | ||
187 | 2006 | Novel full-chip gridless routing considering double-via insertion | Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG | Design Automation Conference | 31 | 0 | |
188 | 2006 | Floorplan and power/ground network co-synthesis for fast design convergence | Liu, C.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 22 | ||
189 | 2006 | Inductance extraction for general interconnect structures | Lai, C.-Y.; Jeng, S.-K.; Chang, Y.-W.; Tsai, C.-C.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 0 | ||
190 | 2006 | Voltage Island aware floorplanning for power and timing optimization | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 74 | 0 | |
191 | 2006 | Modern floorplanning based on B*-tree and fast simulated annealing | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 117 | 79 | |
192 | 2006 | A high-quality mixed-size analytical placer considering preplaced blocks and density constraints | Chen, T.-C.; Jiang, Z.-W.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 62 | 0 | |
193 | 2006 | NTUplace2: A hybrid placer using partitioning and analytical techniques | Jiang, Z.-W.; Chen, T.-C.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 24 | ||
194 | 2006 | Physical design for System-On-a-Chip | Chang, Y.-W.; Chen, T.-C.; Chen, H.-Y.; YAO-WEN CHANG | Essential Issues in SOC Design: Designing Complex Systems-on-Chip | 1 | 0 | |
195 | 2006 | An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles | Su, B.-Y.; Chang, Y.-W.; Hu, J.; YAO-WEN CHANG | International Symposium on Physical Design | 7 | ||
196 | 2005 | Multilevel full-chip routing with testability and yield enhancement | Li, K.S.-M.; Lee, C.-L.; Chang, Y.-W.; Su, C.; Chen, J.-E.; YAO-WEN CHANG | International Workshop on System Level Interconnect Prediction, SLIP | 2 | ||
197 | 2005 | Modern floorplanning based on fast simulated annealing | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 59 | ||
198 | 2005 | TCG: A transitive closure graph-based representation for general floorplans | Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 48 | 37 | |
199 | 2005 | Rlc coupling-Aware simulation for on-chip buses and their encoding for delay reduction | Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 6 | 0 | |
200 | 2005 | Delay modeling for buffered RLY/RLC trees | Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG | 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test | 14 | 0 | |
201 | 2005 | NTUplace: A ratio partitioning based placement algorithm for large-scale mixed-size designs | Chen, T.-C.; Hsu, T.-C.; Jiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 50 | ||
202 | 2005 | Crosstalk- and performance-driven multilevel full-chip routing | Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.-T.; YAO-WEN CHANG ; SAO-JIE CHEN | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 48 | 33 | |
203 | 2005 | IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs | Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 43 | 0 | |
204 | 2005 | Multilevel full-chip gridless routing considering optical proximity correction | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 20 | ||
205 | 2004 | A reusable methodology for non-slicing floorplanning | Hsu, J.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS | 1 | ||
206 | 2004 | Layout techniques for on-chip interconnect inductance reduction | Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 1 | ||
207 | 2004 | Efficient power/ground network analysis for power integrity-driven design methodology | Wu, S.-W.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 21 | ||
208 | 2004 | Multilevel routing with jumper insertion for antenna avoidance | Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG | IEEE International SOC Conference | 1 | ||
209 | 2004 | TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans | Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 44 | 23 | |
210 | 2004 | Universal switch blocks for three-dimensional FPGA design | Wu, G.-M.; Shyu, M.; Chang, Y.-W.; YAO-WEN CHANG | IEE Proceedings: Circuits, Devices and Systems | 9 | 7 | |
211 | 2004 | RLC effects on worst-case switching pattern for on-chip buses | Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 10 | ||
212 | 2004 | Placement with alignment and performance constraints using the B*-tree representation | Wu, M.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 15 | 0 | |
213 | 2004 | Integrating buffer planning with floorplanning for simultaneous multi-objective optimization | Cheng, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 8 | ||
214 | 2004 | Temporal floorplanning using the T-tree formulation | Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 62 | ||
215 | 2004 | Temporal floorplanning using 3D-subTCG | Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; Chen, H.-L.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 42 | ||
216 | 2003 | Graph matching-based algorithms for array-based FPGA segmentation design and routing | Lin, J.-M.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 2 | 0 | |
217 | 2003 | Rectilinear block placement using B*-trees | Wu, G.-M.; Chang, Y.-C.; Chang, Y.-W.; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 25 | 21 | |
218 | 2003 | A Fast Crosstalk- and Performance-Driven Multilevel Routing System | Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.T.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 46 | ||
219 | 2003 | Simultaneous floorplanning and buffer block planning | Hui-Ru Jiang, I.; Chang, Y.-W.; Jou, J.-Y.; Chao, K.-Y.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 11 | 0 | |
220 | 2003 | Multilevel floorplanning/placement for large-scale modules using B*-trees | Lee, H.-C.; Chang, Y.-W.; Hsu, J.-M.; Yang, H.H.; YAO-WEN CHANG | Design Automation Conference | 28 | ||
221 | 2002 | Arbitrarily shaped rectilinear module placement using the transitive closure graph representation | Lin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 8 | 9 | |
222 | 2002 | Inductance modeling for on-chip interconnects | Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG | Proceedings - IEEE International Symposium on Circuits and Systems | 2 | 0 | |
223 | 2002 | Inductance modeling for on-chip interconnects | Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 2 | ||
224 | 2002 | Performance-driven placement for dynamically reconfigurable FPGAs | Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 0 | 0 | |
225 | 2002 | Comment on "generic universal switch blocks" | Fan, H.; Wu, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computers | 6 | 6 | |
226 | 2002 | Arbitrary convex and concave rectilinear module packing using TCG | Lin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG | Design, Automation and Test in Europe, DATE | 6 | 0 | |
227 | 2002 | A novel framework for multilevel routing considering routability and performance | Lin, S.-P.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 55 | 0 | |
228 | 2001 | Performance optimization by wire and buffer sizing under the transmission line model | Chen, T.-C.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 3 | ||
229 | 2001 | Generic ILP-based approaches for dynamically reconfigurable FPGA partitioning | Wu, G.-M.; Lin, J.-M.; Chao, M.C.-T.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors | 0 | 0 | |
230 | 2001 | An algorithm for dynamically reconfigurable FPGA placement | Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors | 6 | 0 | |
231 | 2001 | Generic ILP-based approaches for time-multiplexed FPGA partitioning | Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 30 | 22 | |
232 | 2000 | B * -trees: A new representation for non-slicing floorplans | Chang, Y.-C.; Chang, Y.-W.; Wu, G.-M.; Wu, S.-W.; YAO-WEN CHANG | Proceedings-Design Automation Conference | 466 | 0 | |
233 | 2000 | Generic universal switch blocks | Shyu, M.; Wu, G.-M.; Chang, Y.-D.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computers | 32 | 28 | |
234 | 1999 | Quasi-universal switch matrices for FPD design | Wu, G.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computers | 6 | 3 | |
235 | 1997 | Algorithms for an FPGA switch module routing problem with application to global routing | Thakur, S.; Chang, Y.-W.; Wong, D.F.; Muthukrishnan, S.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | 7 |