第 1 到 107 筆結果,共 107 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
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1 | 2019 | Multiview Contouring for Breast Tumor on Magnetic Resonance Imaging. | Chen, Dar-Ren; Chang, Yao-Wen; Wu, Hwa-Koon; Shia, Wei-Chung; Huang, Yu-Len; YAO-WEN CHANG | J. Digital Imaging | 5 | 4 | |
2 | 2019 | A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. | Hsu, Chen-Hao; Hung, Shao-Chun; Chen, Hao; Sun, Fan-Keng; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019 | 0 | 0 | |
3 | 2019 | BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement. | Sun, Fan-Keng; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019 | 0 | 0 | |
4 | 2018 | beta-Nitrostyrene derivatives attenuate LPS-mediated acute lung injury via the inhibition of neutrophil-platelet interactions and NET release | Chang, Yao-Wen; Tseng, Ching-Ping; Lee, Chih-Hsun; Hwang, Tsong-Long; Chen, Yu-Li; Su, Mei-Tzu; Chong, Kowit-Yu; Lan, Ying-Wei; Wu, Chin-Chung; Chen, Kung-Ju; Lu, Fen-Hua; Liao, Hsiang-Ruei; Hsueh, Chuen; Hsieh, Pei-Wen; YAO-WEN CHANG | American Journal of Physiology-Lung Cellular and Molecular Physiology | 10 | 9 | |
5 | 2017 | An Interview With Professor Chenming Hu, Father of 3D Transistors | Chang, Yao-Wen; Hu, Chenming; YAO-WEN CHANG | Ieee Design & Test | 0 | 0 | |
6 | 2017 | Editorial. | Chakrabarty, Krishnendu; Alioto, Massimo; Baas, Bevan M.; Boon, Chirn Chye; Chang, Meng-Fan; Chang, Naehyuck; Chang, Yao-Wen; Chang, Chip-Hong; Chang, Shih-Chieh; Chen, Poki; Chowdhury, Masud H.; Corsonello, Pasquale; Elfadel, Ibrahim Abe M.; Hamdioui, Said; Hashimoto, Masanori; Ho, Tsung-Yi; Homayoun, Houman; Hwang, Yuh-Shyan; Joshi, Rajiv V.; Karnik, Tanay; Kermani, Mehran Mozaffari; Kim, Chulwoo; Kim, Tae-Hyoung; Kulkarni, Jaydeep P.; Kursun, Eren; Larsson, Erik; Li, Hai (Helen); Li, Huawei; Mercier, Patrick P.; Mishra, Prabhat; Nagata, Makoto; Natarajan, Arun S.; Nii, Koji; Pande, Partha Pratim; Savidis, Ioannis; Seok, Mingoo; Tan, Sheldon X.-D.; Tehranipoor, Mark Mohammad; Todri-Sanial, Aida; Velev, Miroslav N.; Wen, Xiaoqing; Xu, Jiang; Zhang, Wei; Zhang, Zhengya; Jackson, Stacey Weber; YAO-WEN CHANG | IEEE Trans. VLSI Syst. | 0 | 0 | |
7 | 2016 | Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process | Liu, Iou-Jen; Fang, Shao-Yun; Chang, Yao-Wen; YAO-WEN CHANG | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 6 | 5 | |
8 | 2015 | Identification of a novel platelet antagonist that binds to CLEC-2 and suppresses podoplanin-induced platelet aggregation and cancer metastasis | Chang, Yao-Wen; Hsieh, Pei-Wen; Chang, Yu-Tsui; Lu, Meng-Hong; TUR-FU HUANG ; Chong, Kowit-Yu; Liao, Hsiang-Ruei; Cheng, Ju-Chien; YAO-WEN CHANG | Oncotarget | 74 | 62 | |
9 | 2014 | Design and Implementation of a RESTful Notification Service. | Chang, Yao-Wen; Sheu, Ruey-Kai; Jhu, Syuan-Ru; Chang, Yue-Shan; YAO-WEN CHANG | Intelligent Systems and Applications - Proceedings of the International Computer Symposium (ICS) held at Taichung, Taiwan, December 12-14, 2014 | 0 | 0 | |
10 | 2012 | Statistical thermal modeling and optimization considering leakage power variations. | Juan, Da-Cheng; Chuang, Yi-Lin; Marculescu, Diana; Chang, Yao-Wen; YAO-WEN CHANG | 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012 | 0 | 0 | |
11 | 2012 | An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs | Lin, Chung-Wei; Lee, Po-Wei; Chang, Yao-Wen; Shen, Chin-Fang; YAO-WEN CHANG ; CHUNG-WEI LIN | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 16 | 14 | |
12 | 2011 | TSV-aware analytical placement for 3D IC designs. | Hsu, Meng-Kai; Chang, Yao-Wen; Balabanov, Valeriy; YAO-WEN CHANG | Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 | 77 | 0 | |
13 | 2010 | Design of an Omnidirectional Multibeam Transmitter for High-Speed Indoor Wireless Communications. | Tang, Jaw-Luen; Chang, Yao-Wen; YAO-WEN CHANG | EURASIP J. Wireless Comm. and Networking | 3 | 0 | |
14 | 2010 | Recent research development in flip-chip routing. | Lee, Hsu-Chieh; Chang, Yao-Wen; Lee, Po-Wei; YAO-WEN CHANG | 2010 International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, USA, November 7-11, 2010 | 16 | 0 | |
15 | 2009 | An efficient pre-assignment routing algorithm for flip-chip designs. | Lee, Po-Wei; Lin, Chung-Wei; Chang, Yao-Wen; Shen, Chin-Fang; CHUNG-WEI LIN ; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 15 | 0 | |
16 | 2009 | BIST design optimization for large-scale embedded memory cores. | Chien, Tzuo-Fan; Chao, Wen-Chi; Li, James Chien-Mo; Chang, Yao-Wen; Liao, Kuan-Yu; Chang, Ming-Tung; Tsai, Min-Hsiu; CHIEN-MO LI ; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 7 | 0 | |
17 | 2009 | Simultaneous layout migration and decomposition for double patterning technology. | Hsu, Chin-Hsiung; Chang, Yao-Wen; Nassif, Sani R.; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 26 | 0 | |
18 | 2009 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. | Chuang, Yi-Lin; Lee, Po-Wei; Chang, Yao-Wen; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 4 | 0 | |
19 | 2009 | Thermal-driven analog placement considering device matching. | Lin, Mark Po-Hung; Zhang, Hongbo; Wong, Martin D. F.; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009 | 26 | 0 | |
20 | 2008 | Full-Chip Routing Considering Double-Via Insertion | Chen, Huang-Yu; Chiang, Mei-Fang; Chang, Yao-Wen ; Chen, Lumdo; Han, B. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 46 | ||
21 | 2008 | A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning | Chen, Tung-Chieh; Chang, Yao-Wen ; Lin, Shyh-Chang | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 24 | ||
22 | 2008 | Effective Wire Models for X-Architecture Placement | Chen, Tung-Chieh; Chuang, Yi-Lin; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | ||
23 | 2008 | Packing Floorplan Representations. | Chen, Tung-Chieh; Chang, Yao-Wen; YAO-WEN CHANG | Handbook of Algorithms for Physical Design Automation. | |||
24 | 2008 | Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. | Jiang, Zhe-Wei; Su, Bor-Yiing; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008 | 0 | 0 | |
25 | 2008 | Predictive formulae for OPC with applications to lithography-friendly routing. | Chen, Tai-Chen; Liao, Guang-Wan; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008 | 0 | 0 | |
26 | 2008 | A progressive-ILP based routing algorithm for cross-referencing biochips | Yuh, Ping-Hung; Sapatnekar, S.; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG ; CHIA-LIN YANG | Design Automation Conference | 69 | 0 | |
27 | 2008 | An efficient graph-based algorithm for ESD current path analysis | Liu, Chih-Hung; Liu, Hung-Yi; Lin, Chung-Wei; Chou, Szu-Jui; Chang, Yao-Wen; Kuo, Sy-Yen; Yuan, Shih-Yi; CHUNG-WEI LIN ; CHIH-HUNG LIU ; YAO-WEN CHANG ; SY-YEN KUO | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 7 | 4 | |
28 | 2007 | Multilevel Full-Chip Routing With Testability and Yield Enhancement | Li, Katherine Shu-Min; Chang, Yao-Wen ; Lee, Chung-Len; Su, Chauchin; Chen, Jwu E. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 5 | ||
29 | 2007 | Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence | Liu, Chen-Wei; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | ||
30 | 2007 | MB^*-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design | Lee, Hsun-Cheng; Chang, Yao-Wen ; Yang, Hannah Honghua | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
31 | 2007 | Full-Chip Nanometer Routing Techniques. | Ho, Tsung-Yi; Chang, Yao-Wen; Chen, Sao-Jie; YAO-WEN CHANG | ||||
32 | 2007 | NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs. | Chen, Tung-Chieh; Jiang, Zhe-Wei; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG | Modern Circuit Placement, Best Practices and Results | |||
33 | 2007 | MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. | Chen, Tung-Chieh; Yuh, Ping-Hung; Chang, Yao-Wen; Huang, Fwu-Juh; Liu, Denny; YAO-WEN CHANG | Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007 | 0 | 0 | |
34 | 2007 | Efficient obstacle-avoiding rectilinear steiner tree construction. | Lin, Chung-Wei; Chen, Szu-Yu; Li, Chi-Feng; Chang, Yao-Wen; YAO-WEN CHANG ; CHIA-LIN YANG ; CHUNG-WEI LIN | Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007 | 36 | 0 | |
35 | 2007 | An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. | Lee, Wan-Ping; Liu, Hung-Yi; Chang, Yao-Wen; YAO-WEN CHANG | 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007 | 57 | 0 | |
36 | 2007 | An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. | Fang, Jia-Wei; Hsu, Chin-Hsiung; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007 | 0 | 0 | |
37 | 2007 | 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design | Chien, hao-Yi; Shih, Chi-Sheng ; Ku, Mong-Kai; Yang, Chia-Lin ; Chang, Yao-Wen ; Kuo, Tei-Wei ; Chen, Liang-Gee | 2007 IEEE International Conference on Multimedia and Expo, ICME 2007 | 0 | ||
38 | 2007 | Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction | Chen, Tai-Chen; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | ||
39 | 2007 | An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing | Su, Bor-Yiing; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 5 | ||
40 | 2007 | A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages. | Liu, Hung-Yi; Lee, Wan-Ping; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007 | 0 | 0 | |
41 | 2007 | 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. | Chien, Shao-Yi; Shih, Chi-Sheng; Ku, Mong-Kai; Yang, Chia-Lin; Chang, Yao-Wen; Kuo, Tei-Wei; CHIA-LIN YANG ; CHI-SHENG SHIH ; TEI-WEI KUO ; LIANG-GEE CHEN ; YAO-WEN CHANG ; SHAO-YI CHIEN | Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007, July 2-5, 2007, Beijing, China | 0 | 0 | |
42 | 2007 | A Network-Flow-Based RDL Routing Algorithm for Flip-Chip Design | Fang, Jia-Wei; Lin, I-Jye; Chang, Yao-Wen ; Wang, Jyh-Herng | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
43 | 2006 | Inductance extraction for general interconnect structures | Lai, Chun-Ying; Jeng, Shyh-Kang ; Chang, Yao-Wen ; Tsai, Chia-Chun | International Symposium on Circuits and Systems, 2006. ISCAS '06 | 0 | 0 | |
44 | 2006 | Modern Floorplanning Based on B?-Tree and Fast Simulated Annealing | Chen, Tung-Chieh; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
45 | 2006 | A novel framework for multilevel full-chip gridless routing | Chen, Tai-Chen; Chang, Yao-Wen ; Lin, Shyh-Chang | Asia and South Pacific Conference on Design Automation, 2006. | 0 | 0 | |
46 | 2006 | Current path analysis for electrostatic discharge protection. | Liu, Hung-Yi; Lin, Chung-Wei; Chou, Szu-Jui; Tu, Wei-Ting; Liu, Chih-Hung; Chang, Yao-Wen; CHUNG-WEI LIN ; SY-YEN KUO ; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
47 | 2006 | An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. | Su, Bor-Yiing; Chang, Yao-Wen; Hu, Jiang; YAO-WEN CHANG | Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006 | 7 | 0 | |
48 | 2006 | An optimal simultaneous diode/jumper insertion algorithm for antenna fixing. | Jiang, Zhe-Wei; Chang, Yao-Wen; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
49 | 2006 | Placement of digital microfluidic biochips using the T-tree formuation | Yuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen | 43rd annual Design Automation Conference | |||
50 | 2006 | Voltage island aware floorplanning for power and timing optimization. | Lee, Wan-Ping; Liu, Hung-Yi; Chang, Yao-Wen; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
51 | 2006 | A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. | Chen, Tung-Chieh; Jiang, Zhe-Wei; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
52 | 2006 | NTUplace2: a hybrid placer using partitioning and analytical techniques. | Jiang, Zhe-Wei; Chen, Tung-Chieh; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006 | 0 | 0 | |
53 | 2006 | Novel Full-Chip Gridless Routing Considering Double-Via Insertion | Chen, Huang-Yu; Chiang, Mei-Fang; Chang, Yao-Wen ; Chen, Lumdo; Han, Brian | ||||
54 | 2006 | Reliable crosstalk-driven interconnect optimization. | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG | ACM Trans. Design Autom. Electr. Syst. | 0 | 2 | |
55 | 2006 | Floorplan and power/ground network co-synthesis for fast design convergence. | Liu, Chen-Wei; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006 | 22 | 0 | |
56 | 2005 | Crosstalk- and Performance-Driven Multilevel Full-Chip Routing | Ho, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-Jie ; Lee, Der-Tsai | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
57 | 2005 | SoC test scheduling using the B*-tree based floorplanning technique | Wuu, Jen-Yi; Chen, Tung-Chieh; Chang, Yao-Wen | Asia and South Pacific Design Automation Conference, ASP-DAC 2005 | 0 | 0 | |
58 | 2005 | Multilevel full-chip routing with testability and yield enhancement. | Li, Katherine Shu-Min; Lee, Chung-Len; Chang, Yao-Wen; Su, Chauchin; Chen, Jwu E.; YAO-WEN CHANG | The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings | 2 | 0 | |
59 | 2005 | NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. | Chen, Tung-Chieh; Hsu, Tien-Chang; Jiang, Zhe-Wei; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005 | 0 | 0 | |
60 | 2005 | Multilevel full-chip routing for the X-based architecture | Ho, Tsung-Yi; Chang, Chen-Feng; Chang, Yao-Wen ; Chen, Sao-Jie | Design Automation Conference | |||
61 | 2005 | Multilevel full-chip gridless routing considering optical proximity correction. | Chen, Tai-Chen; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005 | 20 | 0 | |
62 | 2005 | Modern floorplanning based on fast simulated annealing. | Chen, Tung-Chieh; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005 | 59 | 0 | |
63 | 2005 | Multilevel routing with antenna avoidance | Ho, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-Jie | Bulletin of the College of Engineering | |||
64 | 2005 | TCG: A transitive closure graph based representation for general floorplans | Lin, Jai-Ming; Chang, Yao-Wen | IEEE Transactions on | |||
65 | 2004 | Temporal floorplanning using the T-tree formulation | Yuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen | IEEE/ACM International Conference on Computer Aided Design, ICCAD-2004. | |||
66 | 2004 | Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. | Cheng, Yi-Hui; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |
67 | 2004 | Timing modeling and optimization under the transmission line model | Chen, Tai-Chen; Pan, Song-Ra; Chang, Yao-Wen | IEEE Transactions on | 32 | 27 | |
68 | 2004 | Layout techniques for on-chip interconnect inductance reduction. | Tu, Shang-Wei; Jou, Jing-Yang; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |
69 | 2004 | Multilevel routing with jumper insertion for antenna avoidance | Ho, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-Jie | IEEE International SOC Conference | 0 | 0 | |
70 | 2004 | Efficient power/ground network analysis for power integrity-driven design methodology. | Wu, Su-Wei; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004 | 21 | 0 | |
71 | 2004 | Temporal Floorplanning Using 3D-subTCG | Yuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen ; Chen, Hsin-Lung | Asia and South Pacific Design Automation Conference, ASP-DAC | |||
72 | 2004 | TCG-S: Orthogonal Coupling of P^*-Admissible Representations for General Floorplans | Lin, Jai-Ming; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
73 | 2004 | Temporal floorplanning using 3D-subTCG. | Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |
74 | 2003 | Inductance Modeling for On-Chip Interconnects | Tu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen ; Chen, Tai-Chen; Jou, Jing-Yang | Analog Integrated Circuits and Signal Processing | 5 | 4 | |
75 | 2003 | A fast crosstalk- and performance-driven multilevel routing system | Ho, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-Jie ; Lee, D.T. | IEEE/ACM International Conference on Computer-Aided Design | 0 | 0 | |
76 | 2003 | Graph matching-based algorithms for array-based FPGA segmentation design and routing. | Lin, Jai-Ming; Pan, Song-Ra; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003 | 0 | 0 | |
77 | 2003 | Multilevel floorplanning/placement for large-scale modules using B*-trees. | Lee, Hsun-Cheng; Chang, Yao-Wen; Hsu, Jer-Ming; Yang, Hannah Honghua; YAO-WEN CHANG | Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003 | 0 | 0 | |
78 | 2003 | Simultaneous floorplanning and buffer block planning. | Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003 | 0 | 0 | |
79 | 2002 | Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. | Chang, Nicholas Chia-Yuan; Chang, Yao-Wen; YAO-WEN CHANG ; HUI-RU JIANG | 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002 | 1 | 0 | |
80 | 2002 | Performance-driven placement for dynamically reconfigurable FPGAs | Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 0 | 0 | |
81 | 2002 | TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. | Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002 | 0 | 0 | |
82 | 2002 | Comment on "Generic universal switch blocks" | Fan, Hongbing; Wu, Yu-Liang; Chang, Yao-Wen | IEEE Transactions on Computers | |||
83 | 2001 | TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. | Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001 | 0 | 0 | |
84 | 2000 | Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. | Pan, Song-Ra; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000 | 0 | 0 | |
85 | 2000 | Optimal reliable crosstalk-driven interconnect optimization. | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000 | 7 | 0 | |
86 | 2000 | Crosstalk-constrained performance optimization by using wire sizing and perturbation | Pan, Song-Ra; Chang, Yao-Wen; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 13 | ||
87 | 2000 | B<sup>*</sup>-trees: a new representation for non-slicing floorplans | Chang, Yun-Chih; Chang, Yao-Wen; Wu, Guang-Ming; Wu, Shu-Wei; YAO-WEN CHANG | Design Automation Conference | 466 | ||
88 | 2000 | Architecture-driven metric for simultaneous placement and global routing for FPGAs | Chang, Yao-Wen; Chang, Yu-Tsang; YAO-WEN CHANG | Design Automation Conference | 12 | ||
89 | 2000 | Rectilinear block placement using B*-trees | Wu, Guang-Ming; Chang, Yun-Chih; Chang, Yao-Wen; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 9 | ||
90 | 2000 | Rectilinear Block Placement Using B*-Trees. | Wu, Guang-Ming; Chang, Yun-Chih; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000 | 0 | 0 | |
91 | 2000 | Timing-driven routing for symmetrical-array-based FPGAs | CHANG, YAO-WEN ; ZHU, KAI; WONG, D. F. | ACM Transactions on Design Automation of Electronic Systems | |||
92 | 2000 | Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. | Jiang, Iris Hui-Ru; Chang, Yao-Wen; YAO-WEN CHANG ; HUI-RU JIANG | IEEE Trans. on CAD of Integrated Circuits and Systems | 49 | 40 | |
93 | 2000 | B*-Trees: a new representation for non-slicing floorplans. | Chang, Yun-Chih; Chang, Yao-Wen; Wu, Guang-Ming; Wu, Shu-Wei; YAO-WEN CHANG | Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000. | 0 | 0 | |
94 | 2000 | Optimal reliable crosstalk-driven interconnect optimization | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG | International Symposium on Physical Design | 7 | ||
95 | 2000 | An architecture-driven metric for simultaneous placement and global routing for FPGAs. | Chang, Yao-Wen; Chang, Yu-Tsang; YAO-WEN CHANG | Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000. | 12 | 0 | |
96 | 1999 | Generic universal switch blocks | Shyu, Michael; Chang, Yu-Dong; Wu, Guang-Ming; Chang, Yao-Wen; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 1 | 0 | |
97 | 1999 | Clustering- and probability-based approach for time-multiplexed FPGA partitioning | Chao, Mango Chia-Tso; Wu, Guang-Ming; Jiang, Iris Hui-Ru; Chang, Yao-Wen; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 17 | ||
98 | 1999 | Universal Switch Blocks for Three-Dimensional FPGA Design. | Wu, Guang-Ming; Shyu, Michael; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, FPGA 1999, Monterey, CA, USA, February 21-23, 1999 | 0 | 0 | |
99 | 1998 | Timing-driven routing for symmetrical-array-based FPGAs. | Zhu, Kai; Chang, Yao-Wen; Wong, D. F.; YAO-WEN CHANG | International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA | 10 | 0 | |
100 | 1998 | Timing-driven routing for symmetrical-array-based FPGAs | Zhu, Kai; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 10 | ||
101 | 1998 | Maximally routable switch matrices for FPD design | Wu, Guang-Min; Chang, Yao-Wen; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 0 | ||
102 | 1996 | Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. | Chen, Chung-Ping; Chang, Yao-Wen; Wong, D. F.; YAO-WEN CHANG | Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996. | 24 | 0 | |
103 | 1996 | Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation | Chen, Chung-Ping; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG | Design Automation Conference | 24 | ||
104 | 1994 | New global routing algorithm for FPGAs | Chang, Yao-Wen; Thakur, Shashidhar; Zhu, Kai; Wong, D.F.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | ||
105 | 1994 | A new global routing algorithm for FPGAs. | Chang, Yao-Wen; Thakur, Shashidhar; Zhu, Kai; Wong, D. F.; YAO-WEN CHANG | Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994 | 0 | 0 | |
106 | 1993 | Switch module design with application to two-dimensional segmentation design. | Zhu, Kai; Wong, D. F.; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993 | 0 | 0 | |
107 | 1993 | Switch module design with application to two-dimensional segmentation design | Zhu, Kai; Wong, D.F.; Chang, Yao-Wen; YAO-WEN CHANG | 15 |