第 1 到 34 筆結果,共 34 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2018 | NTU place4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs with Technology and Region Constraints | Huang, C.-C.; Lee, H.-Y.; Lin, B.-Q.; Yang, S.-W.; Chang, C.-H.; Chen, S.-T.; Chang, Y.-W. ; Chen, T.-C.; Bustany, I. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 34 | 31 | |
2 | 2017 | An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs | Chen, S.-T.; Chang, Y.-W. ; Chen, T.-C. | IEEE/ACM International Conference on Computer-Aided Design | 4 | 0 | |
3 | 2017 | A novel damped-wave framework for macro placement | Chang, C.-H.; Chang, Y.-W. ; Chen, T.-C. | IEEE/ACM International Conference on Computer-Aided Design | 12 | 0 | |
4 | 2017 | Blockage-aware terminal propagation for placement wirelength minimization | Yang, S.-W.; Chang, Y.-W. ; Chen, T.-C. | IEEE/ACM International Conference on Computer-Aided Design | 0 | 0 | |
5 | 2014 | NTUplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designs | Hsu, M.-K.; Chen, Y.-F.; Huang, C.-C.; Chou, S.; Lin, T.-H.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 53 | 51 | |
6 | 2013 | Routability-driven placement for hierarchical mixed-size circuit designs | Hsu, M.-K.; Chen, Y.-F.; Huang, C.-C.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 27 | 0 | |
7 | 2013 | Double patterning lithography-aware analog placement | Chien, H.-C.C.; Ou, H.-C.; Chen, T.-C.; Kuan, T.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 8 | 0 | |
8 | 2010 | Predictive formulae for OPC with applications to lithography-friendly routing | Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | 9 | |
9 | 2009 | Floorplanning | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | Electronic Design Automation | 5 | 0 | |
10 | 2009 | Essential issues in analytical placement algorithms | Chang, Y.-W.; Jiang, Z.-W.; Chen, T.-C.; YAO-WEN CHANG | IPSJ Transactions on System LSI Design Methodology | 34 | 0 | |
11 | 2008 | MP-trees: A packing-based macro placement algorithm for modern mixed-size designs | Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, T.-Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 30 | 27 | |
12 | 2008 | NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints | Chen, T.-C.; Jiang, Z.-W.; Hsu, T.-C.; Chen, H.-C.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 236 | 200 | |
13 | 2008 | Effective wire models for X-architecture placement | Chen, T.-C.; Chuang, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 1 | |
14 | 2008 | Metal-density-driven placement for CMP variation and routability | Chen, T.-C.; Cho, M.; Pan, D.Z.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | 13 | |
15 | 2008 | Predictive formulae for OPC with applications to lithography-friendly routing | Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 20 | 0 | |
16 | 2008 | Metal-density driven placement for CMP variation and routability | Chen, T.-C.; Cho, M.; Pan, D.Z.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 6 | 0 | |
17 | 2008 | A new multilevel framework for large-scale interconnect-driven floorplanning | Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 28 | 25 | |
18 | 2007 | MP-trees: A packing-based macro placement algorithm for mixed-size designs | Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, D.; YAO-WEN CHANG | Design Automation Conference | 14 | 0 | |
19 | 2007 | X-architecture placement based on effective wire models | Chen, T.-C.; Chuang, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 1 | 0 | |
20 | 2007 | Challenges and solutions in modern VLSI placement | Jiang, Z.-W.; Chen, H.-.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | 2007 International Symposium on VLSI Design, Automation and Test | 6 | 0 | |
21 | 2007 | Multilevel full-chip gridless routing with applications to optical-proximity correction | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 13 | |
22 | 2006 | A novel framework for multilevel full-chip gridless routing | Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 14 | ||
23 | 2006 | Modern floorplanning based on B*-tree and fast simulated annealing | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 117 | 79 | |
24 | 2006 | A high-quality mixed-size analytical placer considering preplaced blocks and density constraints | Chen, T.-C.; Jiang, Z.-W.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 62 | 0 | |
25 | 2006 | NTUplace2: A hybrid placer using partitioning and analytical techniques | Jiang, Z.-W.; Chen, T.-C.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 24 | ||
26 | 2006 | Physical design for System-On-a-Chip | Chang, Y.-W.; Chen, T.-C.; Chen, H.-Y.; YAO-WEN CHANG | Essential Issues in SOC Design: Designing Complex Systems-on-Chip | 1 | 0 | |
27 | 2005 | Modern floorplanning based on fast simulated annealing | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 59 | ||
28 | 2005 | NTUplace: A ratio partitioning based placement algorithm for large-scale mixed-size designs | Chen, T.-C.; Hsu, T.-C.; Jiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 50 | ||
29 | 2005 | SoC test scheduling using the B*-tree based floorplanning technique | Wuu, J.-Y.; Chen, T.-C.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 15 | ||
30 | 2005 | IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs | Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 43 | 0 | |
31 | 2005 | Multilevel full-chip gridless routing considering optical proximity correction | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 20 | ||
32 | 2002 | Inductance modeling for on-chip interconnects | Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG | Proceedings - IEEE International Symposium on Circuits and Systems | 2 | 0 | |
33 | 2002 | Inductance modeling for on-chip interconnects | Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 2 | ||
34 | 2001 | Performance optimization by wire and buffer sizing under the transmission line model | Chen, T.-C.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 3 |