第 1 到 453 筆結果,共 453 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2024 | Satisfiability Modulo Theories-Based Qubit Mapping for Trapped-Ion Quantum Computing Systems | Tseng, Wei Hsiang; YAO-WEN CHANG ; Jiang, Jie Hong Roland | Proceedings of the International Symposium on Physical Design | |||
2 | 2024 | Physical Design Challenges in Modern Heterogeneous Integration | YAO-WEN CHANG | Proceedings of the International Symposium on Physical Design | |||
3 | 2023 | Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs | Wei, Min; Tong, Xingyu; Wen, Yuan; Chen, Jianli; Yu, Jun; Zhu, Wenxing; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 0 | 0 | |
4 | 2023 | Security-Aware Physical Design against Trojan Insertion, Frontside Probing, and Fault Injection Attacks | Hsu, Jhih Wei; Chen, Kuan Cheng; Chen, Yan Syuan; Lo, Yu Hsiang; YAO-WEN CHANG | Proceedings of the International Symposium on Physical Design | 0 | 0 | |
5 | 2023 | Late Breaking Results: An Efficient Bridge-based Compression Algorithm for Topologically Quantum Error Corrected Circuits | Tseng, Wei Hsiang; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
6 | 2023 | A General Wavelength-Routed Optical Networks-on-Chip Model with Applications to Provably Good Customized and Fault-Tolerant Topology Designs | Chen, Yan Lin; Tseng, Wei Che; Kao, Wei Yao; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
7 | 2023 | Toward Parallelism-Optimal Topology Generation for Wavelength-Routed Optical NoC Designs | Chen, Kuan Cheng; Chen, Yan Lin; Lu, Yu Sheng; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
8 | 2023 | Floorplanning for Embedded Multi-Die Interconnect Bridge Packages | Lee, Chung Chia; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
9 | 2023 | A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints | Liu, Qinghai; Lin, Disi; Chen, Chuandong; He, Huan; Chen, Jianli; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
10 | 2023 | PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration | Cai, Zhijie; Zou, Peng; Wu, Zhengtao; Tong, Xingyu; Yu, Jun; Chen, Jianli; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
11 | 2023 | Graph-Based Simultaneous Placement and Routing for Two-Dimensional Directed Self-Assembly Technology | Chen, Wei Hsu; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
12 | 2023 | High-performance Placement Engine for Modern Large-scale FPGAs With Heterogeneity and Clock Constraints | Zhu, Ziran; Mei, Yangjie; Deng, Kangkang; He, Huan; Chen, Jianli; Yang, Jun; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | ||
13 | 2023 | Any-Angle Routing for Redistribution Layers in 2.5D IC Packages | Chung, Min Hsuan; Chuang, Je Wei; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
14 | 2023 | Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies | Chen, Yan Jen; Chen, Yan Syuan; Tseng, Wei Che; Chiang, Cheng Yu; Lo, Yu Hsiang; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
15 | 2023 | Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints | Liu, Qinghai; Tang, Qinfei; Chen, Jiarui; Chen, Chuandong; Zhu, Ziran; He, Huan; Chen, Jianli; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
16 | 2022 | Transitive closure graph-based warpage-aware floorplanning for package designs | Hsu, Yang; Chung, Min Hsuan; YAO-WEN CHANG ; Lin, Ci Hong | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
17 | 2022 | SGIRR: Sparse graph index remapping for ReRAM crossbar operation unit and power optimization | Wang, Cheng Yuan; YAO-WEN CHANG ; Chang, Yuan Hao | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
18 | 2022 | Obstacle-avoiding multiple redistribution layer routing with irregular structures | Chen, Yen Ting; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
19 | 2022 | Late Breaking Results: Subgraph Matching Based Reference Placement for PCB Designs | Su, Miaodi; Xiao, Yifeng; Zhang, Shu; Su, Haiyuan; Xu, Jiacen; He, Huan; Zhu, Ziran; Chen, Jianli; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
20 | 2022 | Thermal-aware optical-electrical routing codesign for on-chip signal communications | Lu, Yu Sheng; Chen, Kuan Cheng; Hsu, Yu Ling; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
21 | 2022 | CNN-inspired analytical global placement for large-scale heterogeneous FPGAs | Wang, Huimin; Tong, Xingyu; Ma, Chenyue; Shi, Runming; Chen, Jianli; Wang, Kun; Yu, Jun; YAO-WEN CHANG | Proceedings - Design Automation Conference | 2 | 0 | |
22 | 2022 | Late Breaking Results: Flexible Chip Placement via Reinforcement Learning | Chang, Fu Chieh; Tseng, Yu Wei; Yu, Ya Wen; Lee, Ssu Rui; Cioba, Alexandru; Tseng, I. Lun; Shiu, Da Shan; Hsu, Jhih Wei; Wang, Cheng Yuan; Yang, Chien Yi; Wang, Ren Chu; YAO-WEN CHANG ; Chen, Tai Chen; Chen, Tung Chieh | Proceedings - Design Automation Conference | 0 | 0 | |
23 | 2022 | High-performance placement for large-scale heterogeneous FPGAs with clock constraints | Zhu, Ziran; Mei, Yangjie; Li, Zijun; Lin, Jingwen; Chen, Jianli; Yang, Jun; YAO-WEN CHANG | Proceedings - Design Automation Conference | 2 | 0 | |
24 | 2022 | Y-architecture-based flip-chip routing with dynamic programming-based bend minimization | Nie, Szu Ru; Chen, Yen Ting; YAO-WEN CHANG | Proceedings - Design Automation Conference | 1 | 0 | |
25 | 2022 | A bridge-based algorithm for simultaneous primal and dual defects compression on topologically quantum-error-corrected circuits | Tseng, Wei Hsiang; YAO-WEN CHANG | Proceedings - Design Automation Conference | 1 | 0 | |
26 | 2022 | Mixed-Cell-Height Placement with Drain-to-Drain Abutment and Region Constraints | Chen J; Zhu Z; Guo L; Tseng Y; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 3 | 2 | |
27 | 2022 | Via-based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures | Wen H; Cai Y; Hsu Y; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 0 | |
28 | 2022 | Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification | Bai X; Zhu Z; Zou P; Chen J; Yu J; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 0 | 0 | |
29 | 2022 | A Bridge-based Compression Algorithm for Topological Quantum Circuits | Tseng W; Hsu C; Lin W; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
30 | 2022 | High-Correlation 3D Routability Estimation for Congestion-guided Global Routing | Su M; Ding H; Weng S; Zou C; Zhou Z; Chen Y; Chen J; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 4 | 0 | |
31 | 2021 | Simultaneous Pre-and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias | Cai Y.-J; Hsu Y; YAO-WEN CHANG | Proceedings - Design Automation Conference | 4 | 0 | |
32 | 2021 | Opportunities for 2.5/3D Heterogeneous SoC Integration | CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings | 1 | 0 | |
33 | 2021 | Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems | Chen M.-H; Wang J.-J.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 5 | 0 | |
34 | 2021 | Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot Detection | Wang B; Jiang L; Zhu W; Guo L; Chen J; YAO-WEN CHANG | Proceedings - Design Automation Conference | 1 | 0 | |
35 | 2021 | Timing-Aware Fill Insertions with Design-Rule and Density Constraints | Bai X; Zhu Z; Li P; Chen J; Lan T; Li X; Yu J; Zhu W; Chang Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
36 | 2021 | Analytical Placement Considering the Electron-Beam Fogging Effect | Chen J; Chang Y.-W; Huang Y.-C.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 3 | 3 | |
37 | 2021 | A Bridge-based Compression Algorithm for Topological Quantum Circuits | Hsu C.-H; Lin W.-H; Tseng W.-H; YAO-WEN CHANG | Proceedings - Design Automation Conference | 2 | 0 | |
38 | 2021 | Topological Structure and Physical Layout Co-design for Wavelength-Routed Optical Networks-on-Chip | Lu Y; Chen Y; Yu S; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2 | 2 | |
39 | 2021 | VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units | Chou Y; Hsu J.-W; Chen T.-C.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 3 | 0 | |
40 | 2021 | On-chip Optical Routing with Waveguide Matching Constraints | Chuang F.-Y; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 1 | 0 | |
41 | 2021 | A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization | Chen J; Zhu Z; Zhu W; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 7 | 6 | |
42 | 2021 | A Row-Based Algorithm for Non-Integer Multiple-Cell-Height Placement | Lin Z.-Y; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 2 | 0 | |
43 | 2021 | Time-Division Multiplexing Based System-Level FPGA Routing | Liu W.-K; Chen M.-H; Chang C.-M; Chang C.-C; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
44 | 2021 | On-Chip Optical Routing with Provably Good Algorithms for Path Clustering and Assignment | Lu Y; Yu S; Chang Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
45 | 2021 | A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing | Hsu C.-H; Hung S.-C; Chen H; Sun F.-K; Chang Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 2 | |
46 | 2020 | Time-division multiplexing based system-level FPGA routing for logic verification | Zou, P.; Lin, Z.; Shi, X.; Wu, Y.; Chen, J.; Yu, J.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 5 | 0 | |
47 | 2020 | An efficient EPIST algorithm for global placement with non-integer multiple-height cells | Chen, J.; Huang, Z.; Huang, Y.; Zhu, W.; Yu, J.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 3 | 0 | |
48 | 2020 | Hamiltonian path based mixed-cell-height legalization for neighbor diffusion effect mitigation | Chen, J.; Zhu, Z.; Liu, Q.; Zhang, Y.; Zhu, W.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 4 | 0 | |
49 | 2020 | A provably good wavelength-division-multiplexing-aware clustering algorithm for on-chip optical routing | Lu, Y.-S.; Yu, S.-J.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 6 | 0 | |
50 | 2020 | Mixed-Cell-Height Legalization Considering Technology and Region Constraints | Zhu Z; Chen J; Zhu W; Chang Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | 8 | |
51 | 2020 | Routability-Aware Pin Access Optimization for Monolithic 3D Designs* | Wang R.-Y; Chang Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
52 | 2020 | Latch clustering for timing-power co-optimization | Huang, C.-C.; Tellez, G.; Nam, G.-J.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 2 | 0 | |
53 | 2020 | Topological structure and physical layout codesign for wavelength-routed optical networks-on-chip | Lu, Y.-S.; Yu, S.-J.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 6 | 0 | |
54 | 2020 | Via-based redistribution layer routing for InFO packages with irregular pad structures | Wen, H.-T.; Cai, Y.-J.; Hsu, Y.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 7 | 0 | |
55 | 2020 | 高功率直驅式半導體雷射之發展 | 宋育誠; 蘇信嘉; 張耀文; 林士廷; YAO-WEN CHANG | 機械工業雜誌 | |||
56 | 2020 | Clock-Aware Placement for Large-Scale Heterogeneous FPGAs | Chen, J.; Lin, Z.; Kuo, Y.; Huang, C.; Chang, Y.; Chen, S.; Chiang, C.; SY-YEN KUO ; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 14 | 11 | |
57 | 2020 | Unified Redistribution Layer Routing for 2.5D IC Packages | Chiang, C.-H.; Chuang, F.-Y.; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 2 | 0 | |
58 | 2020 | Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration | Jiang I.H.-R; Chang Y.-W; Huang J.-L; CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 5 | 0 | |
59 | 2019 | Many-body theory of optical absorption in doped two-dimensional semiconductors | Chang, Y.-W.; Reichman, D.R.; YAO-WEN CHANG | Physical Review B | 25 | 23 | |
60 | 2019 | Graph-and ILP-based cut redistribution for two-dimensional directed self-assembly | Wang, Z.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 1 | 0 | |
61 | 2019 | DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography | Su, Y.-H.; Chang, Y.-W. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
62 | 2019 | Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. | Alioto, Massimo; Abadir, Magdy S.; Arslan, Tughrul; Boon, Chirn Chye; Burg, Andreas; Chang, Chip-Hong; Chang, Meng-Fan; Chen, Poki; Corsonello, Pasquale; Crovetti, Paolo; Dosho, Shiro; Drechsler, Rolf; Elfadel, Ibrahim Abe M.; Han, Ruonan; Hashimoto, Masanori; Heng, Chun-Huat; Heo, Deukhyoun; Ho, Tsung-Yi; Homayoun, Houman; Hwang, Yuh-Shyan; Joshi, Ajay; Joshi, Rajiv V.; Karnik, Tanay; Kim, Chulwoo; Kim, Tae-Hyoung; Kulkarni, Jaydeep; Kursun, Volkan; Lee, Yoonmyung; Li, Hai Helen; Li, Huawei; Mishra, Prabhat; Mohammad, Baker; Kermani, Mehran Mozaffari; Nagata, Makoto; Nii, Koji; Pande, Partha Pratim; Paul, Bipul C.; Pavlidis, Vasilis F.; Gyvez, Jos? Pineda de; Savidis, Ioannis; Schaumont, Patrick; Sebastiano, Fabio; Sengupta, Anirban; Seok, Mingoo; Stan, Mircea R.; Tehranipoor, Mark M.; Todri-Sanial, Aida; Verhelst, Marian; Vignoli, Valerio; Wen, Xiaoqing; Xu, Jiang; Zhang, Wei; Zhang, Zhengya; Zhou, Jun; Zwolinski, Mark; Weber, Stacey; YAO-WEN CHANG | IEEE Trans. VLSI Syst. | 6 | 6 | |
63 | 2019 | Obstacle-aware group-based length-matching routing for pre-assignment area-I/O flip-chip designs | Chang, Y.-H.; Wen, H.-T.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 3 | 0 | |
64 | 2019 | BiG: A bivariate gradient-based wirelength model for analytical circuit placement | Sunl, F.-K.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 5 | 0 | |
65 | 2019 | Analytical Mixed-cell-height legalization considering average and maximum movement minimization | Li, X.; Chen, J.; Zhu, W.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings of the International Symposium on Physical Design | 14 | 0 | |
66 | 2019 | Multiview Contouring for Breast Tumor on Magnetic Resonance Imaging. | Chen, Dar-Ren; Chang, Yao-Wen; Wu, Hwa-Koon; Shia, Wei-Chung; Huang, Yu-Len; YAO-WEN CHANG | J. Digital Imaging | 5 | 4 | |
67 | 2019 | A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. | Hsu, Chen-Hao; Hung, Shao-Chun; Chen, Hao; Sun, Fan-Keng; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019 | 0 | 0 | |
68 | 2019 | BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement. | Sun, Fan-Keng; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019 | 0 | 0 | |
69 | 2019 | Analytical placement with 3D poisson's equation and ADMM based optimization for large-scale 2.5D heterogeneous FPGAs | Chen J; Zhu W; Yu J; He L; Chang Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 2 | 0 | |
70 | 2019 | Timing-aware fill insertions with design-rule and density constraints | Lan T; Li X; Chen J; Yu J; He L; Dong S; Zhu W; Chang Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 2 | 0 | |
71 | 2019 | A DAG-based algorithm for obstacle-aware topology-matching on-track bus routing | Hsu, C.-H.; Hungz, S.-C.; Chenz, H.; Sunz, F.-K.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 1 | 0 | |
72 | 2019 | MDP-trees: Multi-Domain Macro Placement for Ultra Large-Scale Mixed-Size Designs | Y. C. Liu; T. C. Chen; Y. W. Chang; S. Y. Kuo; Chang, Y.-W. | 24th Asia and South Pacific Design Automation Conference (ASP-DAC 2019) | 4 | 0 | |
73 | 2018 | NTU place4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs with Technology and Region Constraints | Huang, C.-C.; Lee, H.-Y.; Lin, B.-Q.; Yang, S.-W.; Chang, C.-H.; Chen, S.-T.; Chang, Y.-W. ; Chen, T.-C.; Bustany, I. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 34 | 31 | |
74 | 2018 | Generalized augmented lagrangian and its applications to VLSI global placement | Zhu, Z.; Chen, J.; Peng, Z.; Zhu, W.; Chang, Y.-W. | Design Automation Conference | 15 | 0 | |
75 | 2018 | Mixed-cell-height placement with complex minimum-implant-area constraints | Chen, J.; Yang, P.; Li, X.; Zhu, W.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 15 | 0 | |
76 | 2018 | WB-trees: A meshed tree representation for FinFET analog layout designs | Lu, Y.-S.; Chang, Y.-H.; Chang, Y.-W. | Design Automation Conference | 8 | 0 | |
77 | 2018 | Polarized excitons and optical activity in single-wall carbon nanotubes | Chang, Y.-W. ; Jin, B.-Y. | Physical Review B | 1 | 1 | |
78 | 2018 | Provably good max–min-m-neighbor-TSP-based subfield scheduling for electron-beam photomask fabrication | Lin Z.-W; Fang S.-Y; Chang Y.-W; Rao W.-C; CHIEH-HSIUNG KUAN ; Chang, Y.-W. | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2 | 2 | |
79 | 2018 | DSA-Friendly detailed routing considering double patterning and DSA template assignments | Yu, H.-J.; Chang, Y.-W. | Design Automation Conference | 6 | 0 | |
80 | 2018 | Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction | Wang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W. ; Li, J.C.M.; Jiang, J.-H.R.; JIE-HONG JIANG ; CHIEN-MO LI | Design Automation Conference | 5 | 0 | |
81 | 2018 | Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems | Chen, S.-C.; Sun, R.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 16 | 0 | |
82 | 2018 | A multithreaded initial detailed routing algorithm considering global routing guides | Sun, F.-K.; Chen, H.; Chen, C.-Y.; Hsu, C.-H.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 23 | 0 | |
83 | 2018 | Novel proximal group ADMM for placement considering fogging and proximity effects | Chen, J.; Yang, L.; Peng, Z.; Zhu, W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 8 | 0 | |
84 | 2018 | Mixed-cell-height placement considering drain-to-drain abutment | Tseng, Y.-W.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 11 | 0 | |
85 | 2018 | Mixed-cell-height legalization considering technology and region constraints | Zhu, Z.; Li, X.; Chen, Y.; Chen, J.; Zhu, W.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 14 | 0 | |
86 | 2018 | Analytical solution of Poisson's equation and its application to VLSI global placement | Zhu, W.; Huang, Z.; Chen, J.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 13 | 0 | |
87 | 2018 | beta-Nitrostyrene derivatives attenuate LPS-mediated acute lung injury via the inhibition of neutrophil-platelet interactions and NET release | Chang, Yao-Wen; Tseng, Ching-Ping; Lee, Chih-Hsun; Hwang, Tsong-Long; Chen, Yu-Li; Su, Mei-Tzu; Chong, Kowit-Yu; Lan, Ying-Wei; Wu, Chin-Chung; Chen, Kung-Ju; Lu, Fen-Hua; Liao, Hsiang-Ruei; Hsueh, Chuen; Hsieh, Pei-Wen; YAO-WEN CHANG | American Journal of Physiology-Lung Cellular and Molecular Physiology | 10 | 9 | |
88 | 2017 | Pool-boiling heat-transfer enhancement on cylindrical surfaces with hybrid wettable patterns | Kumar C. S.; S.; Chang, Y.W.; PING-HEI CHEN ; YAO-WEN CHANG | Journal of Visualized Experiments | 16 | 12 | |
89 | 2017 | FPGA placement and routing | Chen, S.-C.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 16 | 0 | |
90 | 2017 | Nanowire-Aware Routing Considering High Cut Mask Complexity | Su, Y.-H.; Chang, Y.-W. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 0 | |
91 | 2017 | Generalized force directed relaxation with optimal regions and its applications to circuit placement | Chang, Y.-W. | International Symposium on Physical Design | 1 | 0 | |
92 | 2017 | An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs | Chen, S.-T.; Chang, Y.-W. ; Chen, T.-C. | IEEE/ACM International Conference on Computer-Aided Design | 4 | 0 | |
93 | 2017 | Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs | Chen, J.; Zhu, Z.; Zhu, W.; Chang, Y.-W. | Design Automation Conference | 38 | 0 | |
94 | 2017 | Graph-Based Logic Bit Slicing for Datapath-Aware Placement | Huang, C.-C.; Lin, B.-Q.; Lee, H.-Y.; Chang, Y.-W. ; Wu, K.-S.; Yang, J.-Z. | Design Automation Conference | 7 | 0 | |
95 | 2017 | Fogging Effect Aware Placement in Electron Beam Lithography | Huang, Y.-C.; Chang, Y.-W. | Design Automation Conference | 7 | 0 | |
96 | 2017 | Redistribution layer routing for wafer-level integrated fan-out package-on-packages | Lin, T.-C.; Chi, C.-C.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 9 | 0 | |
97 | 2017 | A novel damped-wave framework for macro placement | Chang, C.-H.; Chang, Y.-W. ; Chen, T.-C. | IEEE/ACM International Conference on Computer-Aided Design | 12 | 0 | |
98 | 2017 | Mixed-cell-height detailed placement considering complex minimum-implant-area constraints | Wu, Y.-Y.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 17 | 0 | |
99 | 2017 | Cut Redistribution with Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts | Lin, Z.-W.; Chang, Y.-W. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
100 | 2017 | Blockage-aware terminal propagation for placement wirelength minimization | Yang, S.-W.; Chang, Y.-W. ; Chen, T.-C. | IEEE/ACM International Conference on Computer-Aided Design | 0 | 0 | |
101 | 2017 | Clock-aware placement for large-scale heterogeneous FPGAs | Kuo, Y.-C.; Huang, C.-C.; Chen, S.-C.; Chiang, C.-H.; Chang, Y.-W. ; Kuo, S.-Y. | IEEE/ACM International Conference on Computer-Aided Design | 12 | 0 | |
102 | 2017 | Theory of charge transport in molecular junctions: Role of electron correlation | Chang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG | Journal of Chemical Physics | 2 | 2 | |
103 | 2017 | An effective legalization algorithm for mixed-cell-height standard cells | Wang, C.-H.; Wu, Y.-Y.; Chen, J.; Chang, Y.-W.; Kuo, S.-Y.; Zhu, W.; SY-YEN KUO ; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 40 | 0 | |
104 | 2017 | An Interview With Professor Chenming Hu, Father of 3D Transistors | Chang, Yao-Wen; Hu, Chenming; YAO-WEN CHANG | Ieee Design & Test | 0 | 0 | |
105 | 2017 | Detailed Placement for Two-Dimensional Directed Self-Assembly Technology | Lin, Z.-W.; Chang, Y.-W. | Design Automation Conference | 3 | 0 | |
106 | 2017 | Effect of heterogeneous wettable structures on pool boiling performance of cylindrical copper surfaces | Sujith Kumar, C.S.; Chang, Y.W. ; PING-HEI CHEN | Applied Thermal Engineering | 60 | 56 | |
107 | 2017 | Editorial. | Chakrabarty, Krishnendu; Alioto, Massimo; Baas, Bevan M.; Boon, Chirn Chye; Chang, Meng-Fan; Chang, Naehyuck; Chang, Yao-Wen; Chang, Chip-Hong; Chang, Shih-Chieh; Chen, Poki; Chowdhury, Masud H.; Corsonello, Pasquale; Elfadel, Ibrahim Abe M.; Hamdioui, Said; Hashimoto, Masanori; Ho, Tsung-Yi; Homayoun, Houman; Hwang, Yuh-Shyan; Joshi, Rajiv V.; Karnik, Tanay; Kermani, Mehran Mozaffari; Kim, Chulwoo; Kim, Tae-Hyoung; Kulkarni, Jaydeep P.; Kursun, Eren; Larsson, Erik; Li, Hai (Helen); Li, Huawei; Mercier, Patrick P.; Mishra, Prabhat; Nagata, Makoto; Natarajan, Arun S.; Nii, Koji; Pande, Partha Pratim; Savidis, Ioannis; Seok, Mingoo; Tan, Sheldon X.-D.; Tehranipoor, Mark Mohammad; Todri-Sanial, Aida; Velev, Miroslav N.; Wen, Xiaoqing; Xu, Jiang; Zhang, Wei; Zhang, Zhengya; Jackson, Stacey Weber; YAO-WEN CHANG | IEEE Trans. VLSI Syst. | 0 | 0 | |
108 | 2016 | Timing-Driven Cell Placement Optimization for Early Slack Histogram Compression | C. C. Huang; Y. C. Liu; Y. S. Lu; Y. C. Kuo; Y. W. Chang; S. Y. Kuo; SY-YEN KUO ; YAO-WEN CHANG | 53th ACM/IEEE Design Automation Conference (DAC-2016) | 9 | 0 | |
109 | 2016 | Fast lithographic mask optimization considering process variation | Su, Y.-H.; Huang, Y.-C.; Tsai, L.-C.; Chang, Y.-W.; Banerjee, S.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 34 | 30 | |
110 | 2016 | Cut redistribution with directed self-assembly templates for advanced 1-D gridded layouts | Lin, Z.-W.; Chang, Y.-W. | Asia and South Pacific Design Automation Conference, ASP-DAC | 16 | 0 | |
111 | 2016 | Provably good max-min-m-neighbor-TSP-based subfield scheduling for electron-beam photomask fabrication | Lin, Z.-W.; Fang, S.-Y.; Chang, Y.-W. ; Rao, W.-C.; CHIEH-HSIUNG KUAN ; YAO-WEN CHANG | 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 | 1 | 0 | |
112 | 2016 | DSA-compliant routing for two-dimensional patterns using block copolymer lithography | Su, Y.-H.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 4 | 0 | |
113 | 2016 | Layout-Dependent Effects-Aware Analytical Analog Placement | Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 44 | 37 | |
114 | 2016 | Simultaneous EUV flare variation minimization and CMP control by coupling-aware dummification | Chiang, H.-J.K.; Liu, C.-Y.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG ; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 5 | 4 | |
115 | 2016 | Minimum-implant-area-aware detailed placement with spacing constraints | Tseng, K.-H.; Chang, Y.-W.; Liu, C.C.C.; YAO-WEN CHANG | Design Automation Conference | 18 | 0 | |
116 | 2016 | Recent research development and new challenges in analog layout synthesis | Lin, M.P.-H.; Chang, Y.-W.; Hung, C.-M.; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 43 | 0 | |
117 | 2016 | Circular-contour-based obstacle-aware macro placement | Chiou, C.-H.; Chang, C.-H.; Chen, S.-T.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 14 | 0 | |
118 | 2016 | Double-patterning aware DSA template guided cut redistribution for advanced 1-D gridded designs | Lin, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 18 | 0 | |
119 | 2016 | Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process | Liu, Iou-Jen; Fang, Shao-Yun; Chang, Yao-Wen; YAO-WEN CHANG | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 6 | 5 | |
120 | 2016 | VCR: Simultaneous via-template and cut-template-aware routing for directed self-assembly technology | Su, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 4 | 0 | |
121 | 2016 | Detailed-routability-driven analytical placement for mixed-size designs with technology and region constraints | Huang, C.-C.; Lee, H.-Y.; Lin, B.-Q.; Yang, S.-W.; Chang, C.-H.; Chen, S.-T.; Chang, Y.-W.; YAO-WEN CHANG | 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 | 17 | 0 | |
122 | 2016 | Redistribution layer routing for integrated fan-out wafer-level chip-scale packages | Lin, B.-Q.; Lin, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 12 | 0 | |
123 | 2016 | QB-trees: Towards an optimal topological representation and its applications to analog layout designs | Wu, I.-P.; Ou, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 12 | 0 | |
124 | 2015 | Layout-dependent-effects-aware analytical analog placement | Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 15 | 0 | |
125 | 2015 | Fast lithographic mask optimization considering process variation | Su, Y.-H.; Huang, Y.-C.; Tsai, L.-C.; Chang, Y.-W.; Banerjee, S.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 9 | 0 | |
126 | 2015 | Non-stitch triple patterning-aware routing based on conflict graph pre-coloring | Hsu, P.-Y.; Chang, Y.-W.; YAO-WEN CHANG | 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 | 8 | 0 | |
127 | 2015 | Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning | Fang, S.-Y.; Tai, Y.-S.; Chang, Y.-W.; YAO-WEN CHANG | 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 | 7 | 0 | |
128 | 2015 | Routing-architecture-aware analytical placement for heterogeneous FPGAS | Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 18 | 0 | |
129 | 2015 | Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAS | Chen, Y.-C.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 27 | 0 | |
130 | 2015 | Nanowire-aware routing considering high cut mask complexity | Su, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 11 | 0 | |
131 | 2015 | Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits | Ho, K.-H.; Ou, H.-C.; Chang, Y.-W.; Tsao, H.-F.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 12 | 11 | |
132 | 2015 | Identification of a novel platelet antagonist that binds to CLEC-2 and suppresses podoplanin-induced platelet aggregation and cancer metastasis | Chang, Yao-Wen; Hsieh, Pei-Wen; Chang, Yu-Tsui; Lu, Meng-Hong; TUR-FU HUANG ; Chong, Kowit-Yu; Liao, Hsiang-Ruei; Cheng, Ju-Chien; YAO-WEN CHANG | Oncotarget | 74 | 62 | |
133 | 2015 | Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography | Ou, H.-C.; Tseng, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 2 | 0 | |
134 | 2015 | EUV and e-beam manufacturability: Challenges and solutions | Chang, Y.-W.; Liu, R.-G.; Fang, S.-Y.; YAO-WEN CHANG | Design Automation Conference | 15 | 0 | |
135 | 2015 | Stitch-aware routing for multiple e-beam lithography | Liu, I.-J.; Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 6 | 6 | |
136 | 2015 | Detailed-Routing-Driven analytical standard-cell placement | Huang, C.-C.; Chiou, C.-H.; Tseng, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 | 18 | 0 | |
137 | 2015 | Foreword | YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | |||
138 | 2014 | Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification | Chi-Yuan Liu; Hui-Ju K. Chiang; Yao-Wen Chang; Jie-Hong R. Jiang; YAO-WEN CHANG ; JIE-HONG JIANG | ACM/IEEE Design Automation Conference (DAC) | 4 | 0 | |
139 | 2014 | Buffered clock tree synthesis considering self-heating effects | Lin, C.-W.; Hsu, T.-H.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Low Power Electronics and Design | 1 | 0 | |
140 | 2014 | Overlay-Aware detailed routing for self-Aligned double patterning lithography using the cut process | Liu, I.-J.; Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 25 | 0 | |
141 | 2014 | Buffered clock tree synthesis considering self-heating effects. | Lin, Chung-Wei; Hsu, Tzu-Hsuan; Shih, Xin-Wei; YAO-WEN CHANG ; CHUNG-WEI LIN | International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014 | 0 | 0 | |
142 | 2014 | Obstacle-avoiding free-assignment routing for flip-chip designs | Ho, Y.-K.; Lee, H.-C.; Lee, W.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 9 | 9 | |
143 | 2014 | A new asynchronous pipeline template for power and performance optimization | Ho, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 8 | 0 | |
144 | 2014 | Simultaneous EUV flare- and CMP-aware placement | Liu, C.-Y.; Chang, Y.-W.; YAO-WEN CHANG | 2014 32nd IEEE International Conference on Computer Design, ICCD 2014 | 5 | 0 | |
145 | 2014 | Nonuniform multilevel analog routing with matching constraints | Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 22 | 18 | |
146 | 2014 | Design and Implementation of a RESTful Notification Service. | Chang, Yao-Wen; Sheu, Ruey-Kai; Jhu, Syuan-Ru; Chang, Yue-Shan; YAO-WEN CHANG | Intelligent Systems and Applications - Proceedings of the International Computer Symposium (ICS) held at Taichung, Taiwan, December 12-14, 2014 | 0 | 0 | |
147 | 2014 | Theory of charge transport in molecular junctions: From Coulomb blockade to coherent tunneling | Chang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG | Journal of Chemical Physics | 4 | 4 | |
148 | 2014 | Functional ECO using metal-configurable gate-array spare cells | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | Design Automation Conference | 1 | 0 | |
149 | 2014 | Routability-driven blockage-aware macro placement | Chen, Y.-F.; Huang, C.-C.; Chiou, C.-H.; Wang, C.-J.; YAO-WEN CHANG | Design Automation Conference | 18 | 0 | |
150 | 2014 | A novel layout decomposition algorithm for triple patterning lithography | Fang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 46 | 43 | |
151 | 2014 | NTUplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designs | Hsu, M.-K.; Chen, Y.-F.; Huang, C.-C.; Chou, S.; Lin, T.-H.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 53 | 51 | |
152 | 2014 | The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 2014 | YAO-WEN CHANG | ||||
153 | 2013 | Multiple chip planning for chip-interposer codesign | Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 28 | 0 | |
154 | 2013 | Graph-based subfield scheduling for electron-beam photomask fabrication | Fang, S.-Y.; Chen, W.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | 7 | |
155 | 2013 | Layer minimization in escape routing for staggered-pin-array PCBs | Ho, Y.-K.; Shih, X.-W.; Chang, Y.-W.; Cheng, C.-K.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 5 | 0 | |
156 | 2013 | Coupling-Aware length-ratio-matching routing for capacitor arrays in analog integrated circuits | Ho, K.-H.; Ou, H.-C.; Tsao, H.-F.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 6 | 0 | |
157 | 2013 | An efficient and effective analytical placer for FPGAs | Lin, T.-H.; Banerjee, P.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 36 | 0 | |
158 | 2013 | Escape routing for staggered-pin-array PCBs | Ho, Y.-K.; Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 12 | 11 | |
159 | 2013 | Symmetrical buffered clock-tree synthesis with supply-voltage alignment | Shih, X.-W.; Hsu, T.-H.; Lee, H.-C.; Chang, Y.-W.; Chao, K.-Y.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 4 | 0 | |
160 | 2013 | Simultaneous analog placement and routing with current flow and current density considerations | Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 28 | 0 | |
161 | 2013 | Stitch-aware routing for multiple e-beam lithography | Fang, S.-Y.; Liu, I.-J.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 9 | 0 | |
162 | 2013 | Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling. | Fang, Shao-Yun; Lin, Chung-Wei; Liao, Guang-Wan; YAO-WEN CHANG ; CHUNG-WEI LIN | International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 2013 | 4 | 0 | |
163 | 2013 | TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average wirelength model | Hsu, M.-K.; Balabanov, V.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 68 | 54 | |
164 | 2013 | Numerical and experimental investigation of polycarbonate vacuum-forming process | Chang, Y.-W.; JUNG-HO CHENG ; YAO-WEN CHANG | Journal of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an | 6 | 6 | |
165 | 2013 | ECO optimization using metal-configurable gate-array spare cells | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2 | 2 | |
166 | 2013 | Routability-driven placement for hierarchical mixed-size circuit designs | Hsu, M.-K.; Chen, Y.-F.; Huang, C.-C.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 27 | 0 | |
167 | 2013 | Double patterning lithography-aware analog placement | Chien, H.-C.C.; Ou, H.-C.; Chen, T.-C.; Kuan, T.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 8 | 0 | |
168 | 2013 | Technical perspective: Circuit placement challenges | YAO-WEN CHANG | Communications of the ACM | 2 | ||
169 | 2012 | Native-conflict and stitch-aware wire perturbation for double patterning technology | Fang, S.-Y.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 20 | 16 | |
170 | 2012 | Non-uniform multilevel analog routing with matching constraints | Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 24 | 0 | |
171 | 2012 | Graph-based subfield scheduling for electron-beam photomask fabrication | Fang, S.-Y.; Chen, W.-Y.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 3 | 0 | |
172 | 2012 | A chip-package-board co-design methodology | Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 4 | 0 | |
173 | 2012 | Statistical thermal modeling and optimization considering leakage power variations | Juan, D.-C.; Chuang, Y.-L.; Marculescu, D.; Chang, Y.-W.; YAO-WEN CHANG | Design, Automation and Test in Europe, DATE | 10 | ||
174 | 2012 | Fast timing-model independent buffered clock-tree synthesis | Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 14 | 10 | |
175 | 2012 | TRECO: Dynamic technology remapping for timing engineering change orders | Ho, K.-H.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG ; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | 8 | |
176 | 2012 | Unified analytical global placement for large-scale mixed-size circuit designs | Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 19 | |
177 | 2012 | Self-interaction correction to GW approximation | Chang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG | Physica Scripta | 4 | 4 | |
178 | 2012 | Obstacle-avoiding free-assignment routing for flip-chip designs | Lee, P.-W.; Lee, H.-C.; Ho, Y.-K.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG | Design Automation Conference | 2 | 0 | |
179 | 2012 | Simultaneous flare level and flare variation minimization with dummification in EUVL | Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 14 | 0 | |
180 | 2012 | Statistical thermal modeling and optimization considering leakage power variations. | Juan, Da-Cheng; Chuang, Yi-Lin; Marculescu, Diana; Chang, Yao-Wen; YAO-WEN CHANG | 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012 | 0 | 0 | |
181 | 2012 | Timing ECO optimization using metal-configurable gate-array spare cells | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | Proceedings - Design Automation Conference | 4 | 0 | |
182 | 2012 | Structure-aware placement for datapath-intensive circuit designs | Chou, S.; Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 31 | 0 | |
183 | 2012 | Timing ECO optimization via B?zier curve smoothing and fixability identification | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 11 | 9 | |
184 | 2012 | Material characterization of polycarbonate near glass transition temperature | JUNG-HO CHENG ; YAO-WEN CHANG | Journal of the Chinese Institute of Engineers, Series A/Chung-kuo Kung Ch'eng Hsuch K'an | 2 | 2 | |
185 | 2012 | A novel layout decomposition algorithm for triple patterning lithography | Fang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG | Design Automation Conference | 47 | 0 | |
186 | 2012 | An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs | Lin, Chung-Wei; Lee, Po-Wei; Chang, Yao-Wen; Shen, Chin-Fang; YAO-WEN CHANG ; CHUNG-WEI LIN | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 16 | 14 | |
187 | 2012 | Correlation effects of πelectrons on the band structures of conjugated polymers using the self-consistent GW approximation with vertex corrections | Chang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG | Journal of Chemical Physics | 7 | 7 | |
188 | 2011 | Heterogeneous B*-trees for analog placement with symmetry and regularity considerations | Chou, P.-Y.; Ou, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 26 | 0 | |
189 | 2011 | Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips | Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 45 | 33 | |
190 | 2011 | Simultaneous functional and timing ECO. | Chang, Hua-Yu; Jiang, Iris Hui-Ru; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 | 17 | 0 | |
191 | 2011 | Timing ECO optimization via B?zier curve smoothing and fixability identification | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design | 2 | 0 | |
192 | 2011 | An EOS-Free PNP-enhanced cascoded NMOSFET structure for high voltage application | Wang, S.-Y.; Chang, Y.-W.; Chen, Y.-Y.; He, C.-W.; Wu, G.-W.; Lu, T.-C.; Chen, K.-C.; Lu, C.-Y.; YAO-WEN CHANG | IEEE International Reliability Physics Symposium | 2 | 0 | |
193 | 2011 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Guest Editorial | Saxena, P.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
194 | 2011 | PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs | Chuang, Y.-L.; Lin, H.-T.; Ho, T.-Y.; Chang, Y.-W.; Marculescu, D.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 7 | 0 | |
195 | 2011 | A corner stitching compliant B-tree representation and its applications to analog placement | Tsao, H.-F.; Chou, P.-Y.; Huang, S.-L.; Chang, Y.-W.; Lin, M.P.-H.; Chen, D.-P.; Liu, D.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 23 | 0 | |
196 | 2011 | Escape routing for staggered-pin-array PCBs | Ho, Y.-K.; Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 11 | 0 | |
197 | 2011 | Hierarchical placement with layout constraints | Lin, M.P.-H.; Chang, Y.-W.; YAO-WEN CHANG | Analog Layout Synthesis: A Survey of Topological Approaches | 3 | 0 | |
198 | 2011 | Thermal-driven analog placement considering device matching | Lin, M.P.-H.; Zhang, H.; Wong, M.D.F.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 26 | 20 | |
199 | 2011 | Proceedings of the International Symposium on Physical Design: Foreword | Chang, Y.-W.; Hu, J.; YAO-WEN CHANG | International Symposium on Physical Design | 0 | ||
200 | 2011 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs | Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 3 | |
201 | 2011 | Pulsed-latch aware placement for timing-integrity optimization | Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 3 | 1 | |
202 | 2011 | Routability-driven analytical placement for mixed-size circuit designs | Hsu, M.-K.; Chou, S.; Lin, T.-H.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 63 | 0 | |
203 | 2011 | A SAT-based routing algorithm for cross-referencing biochips. | Yuh, Ping-Hung; Lin, Cliff Chiung-Yu; Huang, Tsung-Wei; Ho, Tsung-Yi; Yang, Chia-Lin; YAO-WEN CHANG ; CHIA-LIN YANG | 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011 | 10 | 0 | |
204 | 2011 | Simultaneous functional and timing ECO | Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 17 | ||
205 | 2011 | TSV-aware analytical placement for 3D IC designs | Hsu, M.-K.; Chang, Y.-W.; Balabanov, V.; YAO-WEN CHANG | Design Automation Conference | 77 | ||
206 | 2011 | Simultaneous layout migration and decomposition for double patterning technology | Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 17 | |
207 | 2011 | TSV-aware analytical placement for 3D IC designs. | Hsu, Meng-Kai; Chang, Yao-Wen; Balabanov, Valeriy; YAO-WEN CHANG | Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 | 77 | 0 | |
208 | 2011 | Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011 | YAO-WEN CHANG | ||||
209 | 2010 | Effect of Broken Symmetry on the First Hyperpolarizability of a Centrosymmetric Molecule with an Application to Furan-Containing [2.2]Cyclophandiene | Chang, Yao-Wen ; BIH-YAW JIN | Journal of the Chinese Chemical Society | 1 | 1 | |
210 | 2010 | TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders | Kuan-Hsien Ho; Jie-Hong R. Jiang; Yao-Wen Chang; YAO-WEN CHANG ; JIE-HONG JIANG | Asia and South Pacific Design Automation Conference (ASP-DAC'10) | 14 | 9 | |
211 | 2010 | Predictive formulae for OPC with applications to lithography-friendly routing | Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | 9 | |
212 | 2010 | High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees | Shiht, X.-W.; Leet, H.-C.; Hot, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 23 | 0 | |
213 | 2010 | Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis | Falkenstern, P.; Xie, Y.; Chang, Y.-W.; Wang, Y.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 55 | 0 | |
214 | 2010 | ILP-based pin-count aware design methodology for microfluidic biochips | Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 27 | 22 | |
215 | 2010 | Design-hierarchy aware mixed-size placement for routability optimization | Chuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 26 | 0 | |
216 | 2010 | Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips | Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 25 | 0 | |
217 | 2010 | Density gradient minimization with coupling-constrained dummy fill for CMP control | Chen, H.-Y.; Chou, S.-J.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 20 | 0 | |
218 | 2010 | Design of an Omnidirectional Multibeam Transmitter for High-Speed Indoor Wireless Communications. | Tang, Jaw-Luen; Chang, Yao-Wen; YAO-WEN CHANG | EURASIP J. Wireless Comm. and Networking | 3 | 0 | |
219 | 2010 | Pulsed-latch aware placement for timing-integrity optimization | Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 20 | 0 | |
220 | 2010 | Area-I/O flip-chip routing for chip-package co-design considering signal skews | Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 23 | 21 | |
221 | 2010 | Unified analytical global placement for large-scale mixed-size circuit designs | Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 8 | 0 | |
222 | 2010 | Recent research development in flip-chip routing. | Lee, Hsu-Chieh; Chang, Yao-Wen; Lee, Po-Wei; YAO-WEN CHANG | 2010 International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, USA, November 7-11, 2010 | 16 | 0 | |
223 | 2010 | Template-mask design methodology for double patterning technology | Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 2 | 0 | |
224 | 2010 | Native-conflict-aware wire perturbation for double patterning technology | Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 23 | 0 | |
225 | 2010 | Multilayer global routing with via and wire capacity considerations | Hsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 17 | 16 | |
226 | 2010 | Efficient provably good OPC modeling and its applications to interconnect optimization. | Huang, Shih-Lun; Lin, Chung-Wei; YAO-WEN CHANG ; CHUNG-WEI LIN | 28th International Conference on Computer Design, ICCD 2010, 3-6 October 2010, Amsterdam, The Netherlands, Proceedings | 2 | 0 | |
227 | 2010 | Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization | Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 24 | 0 | |
228 | 2010 | Fast timing-model independent buffered clock-tree synthesis | Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 23 | 0 | |
229 | 2010 | Compositional dependence of phase formation mechanisms at the interface between titanium and calcia-stabilized zirconia at 1550°C | Chang, Y.-W.; Lin, C.-C.; YAO-WEN CHANG | Journal of the American Ceramic Society | 29 | 23 | |
230 | 2010 | Redundant-wires-aware ECO timing and mask cost optimization | Fang, S.-Y.; Chien, T.-F.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 15 | 0 | |
231 | 2010 | ECO timing optimization using spare cells and technology remapping | Ho, K.-H.; Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 15 | |
232 | 2010 | Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010 | YAO-WEN CHANG | ||||
233 | 2009 | High-performance global routing with fast overflow reduction | Qien, H.-Y.; Hsu, C.-H.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 62 | 0 | |
234 | 2009 | An efficient pre-assignment routing algorithm for flip-chip designs. | Lee, Po-Wei; Lin, Chung-Wei; Chang, Yao-Wen; Shen, Chin-Fang; CHUNG-WEI LIN ; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 15 | 0 | |
235 | 2009 | Voltage-Island partitioning and floorplanning under timing constraints | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 11 | |
236 | 2009 | An integer-linear-programming-based routing algorithm for flip-chip designs | Fang, J.-W.; Hsu, C.-H.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 45 | 38 | |
237 | 2009 | Global and Detailed Routing | Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Electronic Design Automation | 24 | 0 | |
238 | 2009 | Floorplanning | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | Electronic Design Automation | 5 | 0 | |
239 | 2009 | A progressive-ILP-based routing algorithm for the synthesis of cross-referencing biochips | Yuh, P.-H.; Sapatnekar, S.S.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG ; CHIA-LIN YANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2 | 5 | |
240 | 2009 | BIST design optimization for large-scale embedded memory cores | Chien, T.-F.; Chao, W.-C.; Li, C.-M.; Chang, Y.-W.; Liao, K.-Y.; Chang, M.-T.; Tsai, M.-H.; Tseng, C.-M.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 7 | ||
241 | 2009 | Analog placement based on symmetry-island formulation | Lin, P.-H.; Lin, S.-C.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 72 | 64 | |
242 | 2009 | BIST design optimization for large-scale embedded memory cores. | Chien, Tzuo-Fan; Chao, Wen-Chi; Li, James Chien-Mo; Chang, Yao-Wen; Liao, Kuan-Yu; Chang, Ming-Tung; Tsai, Min-Hsiu; CHIEN-MO LI ; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 7 | 0 | |
243 | 2009 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs | Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 4 | ||
244 | 2009 | Voltage-island partitioning and floorplanning under timing constraints | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 14 | 11 | |
245 | 2009 | Routing for manufacturability and reliability | Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Circuits and Systems Magazine | 8 | 8 | |
246 | 2009 | A novel wire-density-driven full-chip routing system for cmp variation control | Chen, H.-Y.; Chou, S.-J.; Wang, S.-L.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 23 | 21 | |
247 | 2009 | ILP-based pin-count aware design methodology for microfluidic biochips. | Lin, Cliff Chiung-Yu; YAO-WEN CHANG | Proceedings - Design Automation Conference | |||
248 | 2009 | Flip-chip routing with unified area-I/O pad assignments for package-board co-design. | Fang, Jia-Wei; Wong, Martin D. F.; YAO-WEN CHANG | Proceedings - Design Automation Conference | |||
249 | 2009 | Simultaneous layout migration and decomposition for double patterning technology. | Hsu, Chin-Hsiung; Chang, Yao-Wen; Nassif, Sani R.; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 26 | 0 | |
250 | 2009 | Introduction | Stroud, C.E.; Wang, L.T.; Chang, Y.-W.; YAO-WEN CHANG | Electronic Design Automation | 2 | 0 | |
251 | 2009 | Thermal-driven analog placement considering device matching | Lin, P.-H.; Zhang, H.; Wong, M.D.F.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 26 | ||
252 | 2009 | Spare-cell-aware multilevel analytical placement | Jiang, Z.-W.; Hsu, M.-K.; Chao, K.-Y.; YAO-WEN CHANG | Design Automation Conference | 7 | ||
253 | 2009 | T-trees: A tree-based representation for temporal and three-dimensional floorplanning | Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG ; CHIA-LIN YANG | ACM Transactions on Design Automation of Electronic Systems | 6 | 3 | |
254 | 2009 | Analog layout synthesis - Recent advances in topological approaches | Graeb, H.; Balasa, F.; Castro-Lopez, R.; Chang, Y.-W.; Fern; ez, F.V.; Lin, P.-H.; Strasser, M.; YAO-WEN CHANG | Design, Automation and Test in Europe, DATE | 34 | ||
255 | 2009 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. | Chuang, Yi-Lin; Lee, Po-Wei; Chang, Yao-Wen; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 4 | 0 | |
256 | 2009 | A novel hot-electron programming method in a buried diffusion bit-line SONOS memory by utilizing nonequilibrium charge transport | Wang, T.; Tang, C.-J.; Li, C.-W.; Lee, C.-H.; Ou, T.-F.; Chang, Y.-W.; Tsai, W.-J.; Lu, T.-C.; Chen, K.-C.; Lu, C.-Y.; YAO-WEN CHANG | IEEE Electron Device Letters | 0 | 0 | |
257 | 2009 | Thermal-driven analog placement considering device matching. | Lin, Mark Po-Hung; Zhang, Hongbo; Wong, Martin D. F.; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009 | 26 | 0 | |
258 | 2009 | Essential issues in analytical placement algorithms | Chang, Y.-W.; Jiang, Z.-W.; Chen, T.-C.; YAO-WEN CHANG | IPSJ Transactions on System LSI Design Methodology | 34 | 0 | |
259 | 2009 | Simultaneous layout migration and decomposition for double patterning technology | Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 26 | ||
260 | 2009 | Electronic Design Automation | Wang, L.-T.; Chang, Y.-W.; Cheng, K.-T.; YAO-WEN CHANG | Electronic Design Automation | 128 | 0 | |
261 | 2009 | Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs | Lee, W.-P.; Marculescu, D.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 10 | 0 | |
262 | 2009 | An efficient pre-assignment routing algorithm for flip-chip designs | Lee, P.-W.; Lin, C.-W.; Chang, Y.-W.; Shen, C.-F.; Tseng, W.-C.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 15 | ||
263 | 2008 | 奈米IC設計之前瞻電子設計自動化技術-總計畫 (新制多年期第1年) | 張耀文 | ||||
264 | 2008 | 奈米IC設計之前瞻電子設計自動化技術-子計畫五:在奈米製程下考量可製造性和可靠度之實體設計 (新制多年期第1年) | 張耀文 | ||||
265 | 2008 | Obstacle-avoiding rectilinear steiner tree construction based on spanning graphs | Chen, S.-Y.; Li, C.-F.; CHIA-LIN YANG ; CHUNG-WEI LIN ; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 53 | 46 | |
266 | 2008 | Full-chip routing considering double-via insertion | Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 61 | 46 | |
267 | 2008 | An optimal network-flow-based simultaneous diode and jumper insertion algorithm for antenna fixing | Jiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | 5 | |
268 | 2008 | MP-trees: A packing-based macro placement algorithm for modern mixed-size designs | Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, T.-Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 30 | 27 | |
269 | 2008 | NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints | Chen, T.-C.; Jiang, Z.-W.; Hsu, T.-C.; Chen, H.-C.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 236 | 200 | |
270 | 2008 | Sensitivity-based multiple-Vt cell swapping for leakage power reduction | Lee, W.-P.; Liu, H.-Y.; Ho, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT | 1 | 0 | |
271 | 2008 | Multilayer obstacle-avoiding rectilinear steiner tree construction based on spanning graphs | Lin, C.-W.; Huang, S.-L.; Hsu, K.-C.; Lee, M.-X.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 18 | 21 | |
272 | 2008 | Multi-layer global routing considering via and wire capacities | Hsu, C.-H.; Chen, H.-Y.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 28 | 0 | |
273 | 2008 | Effective wire models for X-architecture placement | Chen, T.-C.; Chuang, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 1 | |
274 | 2008 | Constraint graph-based macro placement for modern mixed-size circuit designs | Chen, H.-C.; Chuang, Y.-L.; Chang, Y.-W.; Chang, Y.-C.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 26 | 0 | |
275 | 2008 | Metal-density-driven placement for CMP variation and routability | Chen, T.-C.; Cho, M.; Pan, D.Z.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | 13 | |
276 | 2008 | Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs | Jiang, Z.-W.; Su, B.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 37 | 0 | |
277 | 2008 | Predictive formulae for OPC with applications to lithography-friendly routing | Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 20 | 0 | |
278 | 2008 | Routing for chip-package-board co-design considering differential pairs | Fang, J.-W.; Ho, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 22 | 0 | |
279 | 2008 | A progressive-ILP based routing algorithm for cross-referencing biochips. | Yuh, Ping-Hung; Sapatnekar, Sachin S.; Yang, Chia-Lin; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008 | 0 | 0 | |
280 | 2008 | Packing Floorplan Representations. | Chen, Tung-Chieh; Chang, Yao-Wen; YAO-WEN CHANG | Handbook of Algorithms for Physical Design Automation. | |||
281 | 2008 | Effect of yttria on interfacial reactions between titanium melt and hot-pressed yttria/zirconia composites at 1700°c | Lin, C.-C.; Chang, Y.-W.; Lin, K.-L.; YAO-WEN CHANG | Journal of the American Ceramic Society | 24 | 16 | |
282 | 2008 | Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. | Jiang, Zhe-Wei; Su, Bor-Yiing; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008 | 0 | 0 | |
283 | 2008 | Predictive formulae for OPC with applications to lithography-friendly routing. | Chen, Tai-Chen; Liao, Guang-Wan; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008 | 0 | 0 | |
284 | 2008 | Area-I/O flip-chip routing for chip-package co-design | Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 45 | 0 | |
285 | 2008 | Metal-density driven placement for CMP variation and routability | Chen, T.-C.; Cho, M.; Pan, D.Z.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 6 | 0 | |
286 | 2008 | A new multilevel framework for large-scale interconnect-driven floorplanning | Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 28 | 25 | |
287 | 2008 | A progressive-ILP based routing algorithm for cross-referencing biochips | Yuh, Ping-Hung; Sapatnekar, S.; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG ; CHIA-LIN YANG | Design Automation Conference | 69 | 0 | |
288 | 2008 | An efficient graph-based algorithm for ESD current path analysis | Liu, Chih-Hung; Liu, Hung-Yi; Lin, Chung-Wei; Chou, Szu-Jui; Chang, Yao-Wen; Kuo, Sy-Yen; Yuan, Shih-Yi; CHUNG-WEI LIN ; CHIH-HUNG LIU ; YAO-WEN CHANG ; SY-YEN KUO | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 7 | 4 | |
289 | 2007 | 兆級晶片系統前瞻技術研究-子計畫六:兆級晶片系統實體整合之研究(3/3) | 張耀文 | ||||
290 | 2007 | 車用聚碳酸酯風擋及車窗之設計及熱成形技術研究 | 鄭榮和 ; 張耀文 ; 張智凱; 李聚儒 | ||||
291 | 2007 | Temporal floorplanning using the three-dimensional transitive closure subGraph | Yuh, Ping-Hung; YAO-WEN CHANG ; CHIA-LIN YANG | ACM Transactions on Design Automation of Electronic Systems | 21 | 17 | |
292 | 2007 | Thermal-driven interconnect optimization by simultaneous gate and wire sizing | Lin, Y.-W.; Chang, Y.-W.; YAO-WEN CHANG | 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 | 0 | 0 | |
293 | 2007 | A network-flow-based RDL routing algorithmz for flip-chip design | Fang, J.-W.; Lin, I.-J.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 59 | 44 | |
294 | 2007 | MB*-tree: A multilevel floorplanner for large-scale building-module design | Lee, H.-C.; Chang, Y.-W.; Yang, H.H.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 2 | |
295 | 2007 | MP-trees: A packing-based macro placement algorithm for mixed-size designs | Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, D.; YAO-WEN CHANG | Design Automation Conference | 14 | 0 | |
296 | 2007 | X-architecture placement based on effective wire models | Chen, T.-C.; Chuang, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 1 | 0 | |
297 | 2007 | An efficient algorithm for statistical circuit optimization using Lagrangian relaxation | Lin, I.-J.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 2 | 0 | |
298 | 2007 | ECO timing optimization using spare cells | Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 43 | 0 | |
299 | 2007 | Efficient multi-layer obstacle-avoiding rectilinear steiner tree construction | Lin, C.-W.; Huang, S.-L.; Hsu, K.-C.; Li, M.-X.; YAO-WEN CHANG ; CHUNG-WEI LIN | IEEE/ACM International Conference on Computer-Aided Design | 15 | 0 | |
300 | 2007 | An optimal jumper-insertion algorithm for antenna avoidance/fixing | Su, B.-Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | 5 | |
301 | 2007 | Full-Chip Nanometer Routing Techniques. | Ho, Tsung-Yi; Chang, Yao-Wen; Chen, Sao-Jie; YAO-WEN CHANG | ||||
302 | 2007 | NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs. | Chen, Tung-Chieh; Jiang, Zhe-Wei; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG | Modern Circuit Placement, Best Practices and Results | |||
303 | 2007 | MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. | Chen, Tung-Chieh; Yuh, Ping-Hung; Chang, Yao-Wen; Huang, Fwu-Juh; Liu, Denny; YAO-WEN CHANG | Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007 | 0 | 0 | |
304 | 2007 | X-route: An x-architecture full-chip multilevel router | Chang, C.-F.; Chang, Y.-W.; YAO-WEN CHANG | 20th Anniversary IEEE International SOC Conference | 4 | 0 | |
305 | 2007 | Efficient obstacle-avoiding rectilinear steiner tree construction. | Lin, Chung-Wei; Chen, Szu-Yu; Li, Chi-Feng; Chang, Yao-Wen; YAO-WEN CHANG ; CHIA-LIN YANG ; CHUNG-WEI LIN | Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007 | 36 | 0 | |
306 | 2007 | An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. | Lee, Wan-Ping; Liu, Hung-Yi; Chang, Yao-Wen; YAO-WEN CHANG | 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007 | 57 | 0 | |
307 | 2007 | Multilevel full-chip routing with testability and yield enhancement | Li, K.S.-M.; Chang, Y.-W.; Lee, C.-L.; Su, C.; Chen, J.E.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 10 | 5 | |
308 | 2007 | 3D video applications and intelligent video surveillance camera and its VLSI design | Chien, S.-Y.; Shih, C.-S.; Ku, M.-K.; Yang, C.-L.; Chang, Y.-W.; Kuo, T.-W.; Chen, L.-G.; YAO-WEN CHANG | 2007 IEEE International Conference on Multimedia and Expo, ICME 2007 | 0 | ||
309 | 2007 | An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. | Fang, Jia-Wei; Hsu, Chin-Hsiung; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007 | 0 | 0 | |
310 | 2007 | An exact jumper-insertion algorithm for antenna violation avoidance/fixing considering routing obstacles | Su, B.-Y.; Hu, J.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 5 | 2 | |
311 | 2007 | Challenges and solutions in modern VLSI placement | Jiang, Z.-W.; Chen, H.-.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | 2007 International Symposium on VLSI Design, Automation and Test | 6 | 0 | |
312 | 2007 | Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. | Lin, Chung-Wei; Tsai, Ming-Chao; Lee, Kuang-Yao; Chen, Tai-Chen; Wang, Ting-Chi; YAO-WEN CHANG ; CHUNG-WEI LIN | Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007 | 14 | 0 | |
313 | 2007 | Novel wire density driven full-chip routing for CMP variation control | Chen, H.-Y.; Chou, S.-J.; Wang, S.-L.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 16 | 0 | |
314 | 2007 | Multilevel full-chip gridless routing with applications to optical-proximity correction | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 13 | |
315 | 2007 | A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages. | Liu, Hung-Yi; Lee, Wan-Ping; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007 | 0 | 0 | |
316 | 2007 | Power/ground network and floorplan cosynthesis for fast design convergence | Liu, C.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 13 | |
317 | 2007 | An integer linear programming based routing algorithm for flip-chip design | Fang, J.-W.; Hsu, C.-H.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 51 | 0 | |
318 | 2007 | A statistical approach to the timing-yield optimization of pipeline circuits | Hsu, C.-H.; Chou, S.-J.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG | Lecture Notes in Computer Science | 0 | ||
319 | 2007 | 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. | Chien, Shao-Yi; Shih, Chi-Sheng; Ku, Mong-Kai; Yang, Chia-Lin; Chang, Yao-Wen; Kuo, Tei-Wei; CHIA-LIN YANG ; CHI-SHENG SHIH ; TEI-WEI KUO ; LIANG-GEE CHEN ; YAO-WEN CHANG ; SHAO-YI CHIEN | Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007, July 2-5, 2007, Beijing, China | 0 | 0 | |
320 | 2007 | Statistical circuit optimization considering device andinterconnect process variations | Lin, I.-J.; Ling, T.-Y.; Chang, Y.-W.; YAO-WEN CHANG | International Workshop on System Level Interconnect Prediction, SLIP | 4 | 0 | |
321 | 2007 | A new interference phenomenon in sub-60nm nitride-based flash memory | YAO-WEN CHANG | 22nd IEEE Non-Volatile Semiconductor Memory Workshop | |||
322 | 2006 | Current path analysis for electrostatic discharge protection | Liu, H.-Y.; Lin, C.-W.; Chou, S.-J.; Tu, W.-T.; Liu, C.-H.; Chang, Y.-W.; YAO-WEN CHANG ; SY-YEN KUO ; CHUNG-WEI LIN ; CHIH-HUNG LIU | IEEE/ACM International Conference on Computer-Aided Design | 8 | 0 | |
323 | 2006 | An optimal simultaneous diode/jumper insertion algorithm for antenna fixing | Jiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 4 | 0 | |
324 | 2006 | Charge-based capacitance measurement for bias-dependent capacitance | Chang, Y.-W.; Chang, H.-W.; Lu, T.-C.; King, Y.-C.; Ting, W.; Ku, Y.-H.J.; Lu, C.-Y.; YAO-WEN CHANG | IEEE Electron Device Letters | 44 | 36 | |
325 | 2006 | A novel framework for multilevel full-chip gridless routing | Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 14 | ||
326 | 2006 | Novel full-chip gridless routing considering double-via insertion | Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG | Design Automation Conference | 31 | 0 | |
327 | 2006 | Floorplan and power/ground network co-synthesis for fast design convergence | Liu, C.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 22 | ||
328 | 2006 | Inductance extraction for general interconnect structures | Lai, C.-Y.; Jeng, S.-K.; Chang, Y.-W.; Tsai, C.-C.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 0 | ||
329 | 2006 | RLC coupling-aware simulation and on-chip bus encoding for delay reduction | Tu, S.-W.; Jou, J.-Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 37 | 23 | |
330 | 2006 | Simultaneous block and I/O buffer floorplanning for flip-chip design | Peng, C.-Y.; Chao, W.-C.; Wang, J.-H.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 14 | ||
331 | 2006 | Current path analysis for electrostatic discharge protection. | Liu, Hung-Yi; Lin, Chung-Wei; Chou, Szu-Jui; Tu, Wei-Ting; Liu, Chih-Hung; Chang, Yao-Wen; CHUNG-WEI LIN ; SY-YEN KUO ; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
332 | 2006 | Voltage Island aware floorplanning for power and timing optimization | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 74 | 0 | |
333 | 2006 | Modern floorplanning based on B*-tree and fast simulated annealing | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 117 | 79 | |
334 | 2006 | Placement of digital microfluidic biochips using the t-tree formulation | Yuh, P.-H.; Yang, C.-L.; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings - Design Automation Conference | 44 | 0 | |
335 | 2006 | A high-quality mixed-size analytical placer considering preplaced blocks and density constraints | Chen, T.-C.; Jiang, Z.-W.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 62 | 0 | |
336 | 2006 | IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults | Li, K.S.-M.; Su, C.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 11 | 9 | |
337 | 2006 | NTUplace2: A hybrid placer using partitioning and analytical techniques | Jiang, Z.-W.; Chen, T.-C.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 24 | ||
338 | 2006 | An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. | Su, Bor-Yiing; Chang, Yao-Wen; Hu, Jiang; YAO-WEN CHANG | Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006 | 7 | 0 | |
339 | 2006 | Physical design for System-On-a-Chip | Chang, Y.-W.; Chen, T.-C.; Chen, H.-Y.; YAO-WEN CHANG | Essential Issues in SOC Design: Designing Complex Systems-on-Chip | 1 | 0 | |
340 | 2006 | Multilevel routing with jumper insertion for antenna avoidance | Ho, T.-Y.; YAO-WEN CHANG ; SAO-JIE CHEN | Integration, the VLSI Journal | 5 | 2 | |
341 | 2006 | An optimal simultaneous diode/jumper insertion algorithm for antenna fixing. | Jiang, Zhe-Wei; Chang, Yao-Wen; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
342 | 2006 | Voltage island aware floorplanning for power and timing optimization. | Lee, Wan-Ping; Liu, Hung-Yi; Chang, Yao-Wen; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
343 | 2006 | A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. | Chen, Tung-Chieh; Jiang, Zhe-Wei; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
344 | 2006 | An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles | Su, B.-Y.; Chang, Y.-W.; Hu, J.; YAO-WEN CHANG | International Symposium on Physical Design | 7 | ||
345 | 2006 | NTUplace2: a hybrid placer using partitioning and analytical techniques. | Jiang, Zhe-Wei; Chen, Tung-Chieh; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006 | 0 | 0 | |
346 | 2006 | Reliable crosstalk-driven interconnect optimization. | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG | ACM Trans. Design Autom. Electr. Syst. | 0 | 2 | |
347 | 2006 | Floorplan and power/ground network co-synthesis for fast design convergence. | Liu, Chen-Wei; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006 | 22 | 0 | |
348 | 2006 | IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults | Li, K.S.-M.; Su, C.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 0 | ||
349 | 2005 | Multilevel full-chip routing with testability and yield enhancement | Li, K.S.-M.; Lee, C.-L.; Chang, Y.-W.; Su, C.; Chen, J.-E.; YAO-WEN CHANG | International Workshop on System Level Interconnect Prediction, SLIP | 2 | ||
350 | 2005 | Modern floorplanning based on fast simulated annealing | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 59 | ||
351 | 2005 | TCG: A transitive closure graph-based representation for general floorplans | Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 48 | 37 | |
352 | 2005 | A routing algorithm for flip-chip design | Fang, J.-W.; Lin, I.-J.; Yuh, P.-H.; Wang, J.-H.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 43 | 0 | |
353 | 2005 | Placement with symmetry constraints for analog layout design using TCG-S | Lin, J.-M.; Wu, G.-M.; Chuang, J.-H.; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 43 | ||
354 | 2005 | Rlc coupling-Aware simulation for on-chip buses and their encoding for delay reduction | Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 6 | 0 | |
355 | 2005 | Multilevel full-chip routing with testability and yield enhancement. | Li, Katherine Shu-Min; Lee, Chung-Len; Chang, Yao-Wen; Su, Chauchin; Chen, Jwu E.; YAO-WEN CHANG | The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings | 2 | 0 | |
356 | 2005 | NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. | Chen, Tung-Chieh; Hsu, Tien-Chang; Jiang, Zhe-Wei; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005 | 0 | 0 | |
357 | 2005 | Delay modeling for buffered RLY/RLC trees | Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG | 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test | 14 | 0 | |
358 | 2005 | Multilevel full-chip gridless routing considering optical proximity correction. | Chen, Tai-Chen; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005 | 20 | 0 | |
359 | 2005 | An exact jumper insertion algorithm for antenna effect avoidance/fixing. | Su, Bor-Yiing; YAO-WEN CHANG | Proceedings - Design Automation Conference | 10 | 0 | |
360 | 2005 | NTUplace: A ratio partitioning based placement algorithm for large-scale mixed-size designs | Chen, T.-C.; Hsu, T.-C.; Jiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 50 | ||
361 | 2005 | Multilevel full-chip routing for the X-based architecture. | SAO-JIE CHEN ; Chang, Chen-Feng; YAO-WEN CHANG ; Ho T.-Y | Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005 | 39 | 0 | |
362 | 2005 | Crosstalk- and performance-driven multilevel full-chip routing | Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.-T.; YAO-WEN CHANG ; SAO-JIE CHEN | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 48 | 33 | |
363 | 2005 | Modern floorplanning based on fast simulated annealing. | Chen, Tung-Chieh; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005 | 59 | 0 | |
364 | 2005 | Joint exploration of architectural and physical design spaces with thermal consideration. | Wu, Yen-Wei; Yang, Chia-Lin; Yuh, Ping-Hung; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005 | 18 | 0 | |
365 | 2005 | 多媒體通訊系統中可重組化運算技術之研究─子計畫五:可重組化系統之實體設計(3/3) | 張耀文 | ||||
366 | 2005 | SoC test scheduling using the B*-tree based floorplanning technique | Wuu, J.-Y.; Chen, T.-C.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 15 | ||
367 | 2005 | IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs | Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 43 | 0 | |
368 | 2005 | Multilevel full-chip gridless routing considering optical proximity correction | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 20 | ||
369 | 2004 | 提升鈦合金超塑性成形及擴散接合技術研究(二) | 鄭榮和 ; 張耀文 ; 曾炳瑋 | ||||
370 | 2004 | Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. | Cheng, Yi-Hui; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |
371 | 2004 | A reusable methodology for non-slicing floorplanning | Hsu, J.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS | 1 | ||
372 | 2004 | Layout techniques for on-chip interconnect inductance reduction | Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 1 | ||
373 | 2004 | Efficient power/ground network analysis for power integrity-driven design methodology | Wu, S.-W.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 21 | ||
374 | 2004 | Multilevel routing with jumper insertion for antenna avoidance | Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG | IEEE International SOC Conference | 1 | ||
375 | 2004 | Layout techniques for on-chip interconnect inductance reduction. | Tu, Shang-Wei; Jou, Jing-Yang; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |
376 | 2004 | Multilevel routing with antenna avoidance. | Ho, Tsung-Yi; SAO-JIE CHEN ; YAO-WEN CHANG | Proceedings of the International Symposium on Physical Design | 36 | 0 | |
377 | 2004 | TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans | Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 44 | 23 | |
378 | 2004 | Universal switch blocks for three-dimensional FPGA design | Wu, G.-M.; Shyu, M.; Chang, Y.-W.; YAO-WEN CHANG | IEE Proceedings: Circuits, Devices and Systems | 9 | 7 | |
379 | 2004 | RLC effects on worst-case switching pattern for on-chip buses | Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 10 | ||
380 | 2004 | Efficient power/ground network analysis for power integrity-driven design methodology. | Wu, Su-Wei; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004 | 21 | 0 | |
381 | 2004 | Placement with alignment and performance constraints using the B*-tree representation | Wu, M.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 15 | 0 | |
382 | 2004 | Integrating buffer planning with floorplanning for simultaneous multi-objective optimization | Cheng, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 8 | ||
383 | 2004 | Temporal floorplanning using the T-tree formulation | Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 62 | ||
384 | 2004 | Temporal floorplanning using 3D-subTCG | Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; Chen, H.-L.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 42 | ||
385 | 2004 | Temporal floorplanning using the T-tree formulation. | Yuh, Ping-Hung; Yang, Chia-Lin; CHIA-LIN YANG ; YAO-WEN CHANG | 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004 | 0 | 0 | |
386 | 2004 | Temporal floorplanning using 3D-subTCG. | Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |
387 | 2003 | Noise-aware buffer planning for interconnect-driven floorplanning | Li, S.-M.; Cherng, Y.-H.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 6 | 0 | |
388 | 2003 | Analysis of FPGA/FPIC switch modules | Zhu, K.; Wu, G.-M.; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 2 | 3 | |
389 | 2003 | Graph matching-based algorithms for array-based FPGA segmentation design and routing | Lin, J.-M.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 2 | 0 | |
390 | 2003 | Graph matching-based algorithms for array-based FPGA segmentation design and routing. | Lin, Jai-Ming; Pan, Song-Ra; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003 | 0 | 0 | |
391 | 2003 | Multilevel floorplanning/placement for large-scale modules using B*-trees. | Lee, Hsun-Cheng; Chang, Yao-Wen; Hsu, Jer-Ming; Yang, Hannah Honghua; YAO-WEN CHANG | Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003 | 0 | 0 | |
392 | 2003 | Rectilinear block placement using B*-trees | Wu, G.-M.; Chang, Y.-C.; Chang, Y.-W.; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 25 | 21 | |
393 | 2003 | A Fast Crosstalk- and Performance-Driven Multilevel Routing System | Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.T.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 46 | ||
394 | 2003 | Simultaneous floorplanning and buffer block planning. | Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003 | 0 | 0 | |
395 | 2003 | Simultaneous floorplanning and buffer block planning | Hui-Ru Jiang, I.; Chang, Y.-W.; Jou, J.-Y.; Chao, K.-Y.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 11 | 0 | |
396 | 2003 | Multilevel floorplanning/placement for large-scale modules using B*-trees | Lee, H.-C.; Chang, Y.-W.; Hsu, J.-M.; Yang, H.H.; YAO-WEN CHANG | Design Automation Conference | 28 | ||
397 | 2002 | Module placement with boundary constraints using B*-trees | Lin, J.-M.; Yi, H.-E.; YAO-WEN CHANG | IEE Proceedings: Circuits, Devices and Systems | 18 | 11 | |
398 | 2002 | Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. | Chang, Nicholas Chia-Yuan; Chang, Yao-Wen; YAO-WEN CHANG ; HUI-RU JIANG | 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002 | 1 | 0 | |
399 | 2002 | Arbitrarily shaped rectilinear module placement using the transitive closure graph representation | Lin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 8 | 9 | |
400 | 2002 | Inductance modeling for on-chip interconnects | Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG | Proceedings - IEEE International Symposium on Circuits and Systems | 2 | 0 | |
401 | 2002 | Inductance modeling for on-chip interconnects | Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 2 | ||
402 | 2002 | Performance-driven placement for dynamically reconfigurable FPGAs | Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 0 | 0 | |
403 | 2002 | Comment on "generic universal switch blocks" | Fan, H.; Wu, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computers | 6 | 6 | |
404 | 2002 | Arbitrary convex and concave rectilinear module packing using TCG | Lin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG | Design, Automation and Test in Europe, DATE | 6 | 0 | |
405 | 2002 | A novel framework for multilevel routing considering routability and performance | Lin, S.-P.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 55 | 0 | |
406 | 2002 | TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. | Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002 | 0 | 0 | |
407 | 2001 | Performance optimization by wire and buffer sizing under the transmission line model | Chen, T.-C.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 3 | ||
408 | 2001 | Generic ILP-based approaches for dynamically reconfigurable FPGA partitioning | Wu, G.-M.; Lin, J.-M.; Chao, M.C.-T.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors | 0 | 0 | |
409 | 2001 | An algorithm for dynamically reconfigurable FPGA placement | Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors | 6 | 0 | |
410 | 2001 | Generic ILP-based approaches for time-multiplexed FPGA partitioning | Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 30 | 22 | |
411 | 2001 | TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. | Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001 | 0 | 0 | |
412 | 2000 | Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. | Pan, Song-Ra; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000 | 0 | 0 | |
413 | 2000 | Optimal reliable crosstalk-driven interconnect optimization. | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000 | 7 | 0 | |
414 | 2000 | Timing-driven routing for symmetrical array-based FPGAs | Zhu, K.; Wong, D.F.; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 23 | 20 | |
415 | 2000 | Crosstalk-constrained performance optimization by using wire sizing and perturbation | Pan, Song-Ra; Chang, Yao-Wen; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 13 | ||
416 | 2000 | B<sup>*</sup>-trees: a new representation for non-slicing floorplans | Chang, Yun-Chih; Chang, Yao-Wen; Wu, Guang-Ming; Wu, Shu-Wei; YAO-WEN CHANG | Design Automation Conference | 466 | ||
417 | 2000 | Architecture-driven metric for simultaneous placement and global routing for FPGAs | Chang, Yao-Wen; Chang, Yu-Tsang; YAO-WEN CHANG | Design Automation Conference | 12 | ||
418 | 2000 | Rectilinear block placement using B*-trees | Wu, Guang-Ming; Chang, Yun-Chih; Chang, Yao-Wen; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 9 | ||
419 | 2000 | Rectilinear Block Placement Using B*-Trees. | Wu, Guang-Ming; Chang, Yun-Chih; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000 | 0 | 0 | |
420 | 2000 | B * -trees: A new representation for non-slicing floorplans | Chang, Y.-C.; Chang, Y.-W.; Wu, G.-M.; Wu, S.-W.; YAO-WEN CHANG | Proceedings-Design Automation Conference | 466 | 0 | |
421 | 2000 | Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. | Jiang, Iris Hui-Ru; Chang, Yao-Wen; YAO-WEN CHANG ; HUI-RU JIANG | IEEE Trans. on CAD of Integrated Circuits and Systems | 49 | 40 | |
422 | 2000 | B*-Trees: a new representation for non-slicing floorplans. | Chang, Yun-Chih; Chang, Yao-Wen; Wu, Guang-Ming; Wu, Shu-Wei; YAO-WEN CHANG | Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000. | 0 | 0 | |
423 | 2000 | Generic universal switch blocks | Shyu, M.; Wu, G.-M.; Chang, Y.-D.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computers | 32 | 28 | |
424 | 2000 | Optimal reliable crosstalk-driven interconnect optimization | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG | International Symposium on Physical Design | 7 | ||
425 | 2000 | Crosstalkdriven interconnect optimization by simultaneous gate and wire sizing | Jiang, I.H.R.; Chang, Y.W.; Jou, J.Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 10 | ||
426 | 2000 | An architecture-driven metric for simultaneous placement and global routing for FPGAs. | Chang, Yao-Wen; Chang, Yu-Tsang; YAO-WEN CHANG | Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000. | 12 | 0 | |
427 | 1999 | Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. | Jiang, Iris Hui-Ru; Jou, Jing-Yang; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999. | 9 | 0 | |
428 | 1999 | Quasi-universal switch matrices for FPD design | Wu, G.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computers | 6 | 3 | |
429 | 1999 | Generic universal switch blocks | Shyu, Michael; Chang, Yu-Dong; Wu, Guang-Ming; Chang, Yao-Wen; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 1 | 0 | |
430 | 1999 | A clustering- and probability-based approach for time-multiplexed FPGA partitioning. | Chao, Mango Chia-Tso; Wu, Guang-Ming; Jiang, Iris Hui-Ru; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999 | 0 | 0 | |
431 | 1999 | Clustering- and probability-based approach for time-multiplexed FPGA partitioning | Chao, Mango Chia-Tso; Wu, Guang-Ming; Jiang, Iris Hui-Ru; Chang, Yao-Wen; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 17 | ||
432 | 1999 | Universal Switch Blocks for Three-Dimensional FPGA Design. | Wu, Guang-Ming; Shyu, Michael; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, FPGA 1999, Monterey, CA, USA, February 21-23, 1999 | 0 | 0 | |
433 | 1998 | Timing-driven routing for symmetrical-array-based FPGAs. | Zhu, Kai; Chang, Yao-Wen; Wong, D. F.; YAO-WEN CHANG | International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA | 10 | 0 | |
434 | 1998 | Timing-driven routing for symmetrical-array-based FPGAs | Zhu, Kai; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 10 | ||
435 | 1998 | Switch-matrix architecture and routing for FPDs | Wu, Guang-Min; YAO-WEN CHANG | International Symposium on Physical Design | 2 | ||
436 | 1998 | Maximally routable switch matrices for FPD design | Wu, Guang-Min; Chang, Yao-Wen; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 0 | ||
437 | 1998 | Graph matching-based algorithms for FPGA segmentation design. | Lin, Jai-Ming; Wong, D. F.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers | 7 | 0 | |
438 | 1997 | Graph-theoretic sufficient condition for FPGA/FPIC switch-module routability | Wong, D.F.; Wong, C.K.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 0 | ||
439 | 1997 | Algorithms for an FPGA switch module routing problem with application to global routing | Thakur, S.; Chang, Y.-W.; Wong, D.F.; Muthukrishnan, S.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | 7 | |
440 | 1996 | On a new timing-driven routing tree problem | Wong, D.F.; Zhu, Kai; Wong, C.K.; YAO-WEN CHANG | Proceedings - IEEE International Symposium on Circuits and Systems | 2 | ||
441 | 1996 | Universal switch-module design for symmetric-array-based FPGAs | Wong, D.F.; Wong, C.K.; YAO-WEN CHANG | ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA | 20 | 0 | |
442 | 1996 | Universal switch modules for fpga design | Wong, D.F.; Wong, C.K.; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 103 | ||
443 | 1996 | A velocity-overshoot capacitance model for 0.1 μm MOS transistors | Kuo, J.B.; Chang, Y.W.; Lai, C.S.; YAO-WEN CHANG | Solid-State Electronics | 4 | 4 | |
444 | 1996 | Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. | Chen, Chung-Ping; Chang, Yao-Wen; Wong, D. F.; YAO-WEN CHANG | Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996. | 24 | 0 | |
445 | 1996 | Universal Switch-Module Design for Symmetric-Array-Based FPGAs. | Wong, D. F.; Wong, C. K.; YAO-WEN CHANG | Proceedings of the 1996 ACM 4th International Symposium on Field-Programmable Gate Arrays, FPGA 1996 | 0 | 0 | |
446 | 1996 | An analytical velocity overshoot model for 0.1 μm N-channel metal-oxide-silicon devices considering energy transport | JAMES-B KUO ; YAO-WEN CHANG ; Chen Y.-G. | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers | 1 | 0 | |
447 | 1996 | Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation | Chen, Chung-Ping; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG | Design Automation Conference | 24 | ||
448 | 1995 | FPGA global routing based on a new congestion metric | Wong, D.F.; Wong, C.K.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 13 | ||
449 | 1995 | Design and analysis of FPGA/FPIC switch modules. | Wong, D. F.; Wong, C. K.; YAO-WEN CHANG | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors | 5 | 0 | |
450 | 1994 | New global routing algorithm for FPGAs | Chang, Yao-Wen; Thakur, Shashidhar; Zhu, Kai; Wong, D.F.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | ||
451 | 1994 | A new global routing algorithm for FPGAs. | Chang, Yao-Wen; Thakur, Shashidhar; Zhu, Kai; Wong, D. F.; YAO-WEN CHANG | Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994 | 0 | 0 | |
452 | 1993 | Switch module design with application to two-dimensional segmentation design. | Zhu, Kai; Wong, D. F.; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993 | 0 | 0 | |
453 | 1993 | Switch module design with application to two-dimensional segmentation design | Zhu, Kai; Wong, D.F.; Chang, Yao-Wen; YAO-WEN CHANG | 15 |