第 1 到 120 筆結果,共 120 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2019 | Real-Time Multi-User Detection Engine Design for IoT Applications via Modified Sparsity Adaptive Matching Pursuit | Liao, C.-C.; Chen, T.-S.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems I: Regular Papers | 6 | 4 | |
2 | 2015 | Byte-reconfigurable LDPC codec design with application to high-performance ECC of NAND flash memory systems | Lin, Y.-M.; Li, H.-T.; Chung, M.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems I: Regular Papers | 19 | 17 | |
3 | 2014 | Low-complexity motion-compensated beamforming algorithm and architecture for synthetic transmit aperture in ultrasound imaging | Chen, Y.-H.; Lin, Y.-M.; Ho, K.-Y.; Wu, A.-Y.; Li, P.-C.; PAI-CHI LI ; AN-YEU(ANDY) WU | IEEE Transactions on Signal Processing | 6 | 0 | |
4 | 2014 | Hydra: An energy-efficient programmable cryptographic coprocessor supporting elliptic-curve pairings over fields of large characteristics | Chang, Y.-A.; Hong, W.-C.; Hsiao, M.-C.; Yang, B.-Y.; Wu, A.-Y.; Cheng, C.-M.; CHEN-MOU CHENG ; AN-YEU(ANDY) WU | Lecture Notes in Computer Science | 1 | 0 | |
5 | 2014 | High-throughput QC-LDPC decoder with cost-effective early termination scheme for non-volatile memory systems | Lin, Y.-M.; Chen, Y.-H.; Chung, M.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 3 | 0 | |
6 | 2014 | Spatial-temporal enhancement of ACO-based selection schemes for adaptive routing in network-on-chip systems | Hsin, H.-K.; Chang, E.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Parallel and Distributed Systems | 11 | 8 | |
7 | 2014 | Traffic-and thermal-aware routing algorithms for 3d network-on-chip (3D NoC) systems | Chen, K.-C.; Chao, C.-H.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | Routing Algorithms in Networks-on-Chip | 8 | 0 | |
8 | 2013 | Hybrid path-diversity-aware adaptive routing with latency prediction model in Network-on-Chip systems | Tsai, P.-A.; Kuo, Y.-H.; Chang, E.-J.; Hsin, H.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 | 12 | 0 | |
9 | 2013 | Dual-mode low-complexity codebook searching algorithm and VLSI architecture for LTE/LTE-advanced systems | Lin, Y.-H.; Chen, Y.-H.; Chu, C.-Y.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Signal Processing | 11 | 8 | |
10 | 2013 | Editorial low-power, intelligent, and secure solutions for realization of internet of things | Chen, Y.-K.; Wu, A.-Y.; Bayoumi, M.A.; Koushanfar, F.; AN-YEU(ANDY) WU | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | 7 | 18 | |
11 | 2013 | Design of thermal management unit with vertical throttling scheme for proactive thermal-aware 3D NoC systems | Chen, K.-C.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2013 International Symposium on VLSI Design, Automation, and Test | 10 | 0 | |
12 | 2013 | Accelerating motion-compensated adaptive color Doppler engine on CUDA-based GPU platform | Lee, I.-H.; Chen, Y.-H.; Huang, N.-S.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 1 | 0 | |
13 | 2013 | ACO-based fault-aware routing algorithm for Network-on-Chip systems | Lin, C.-A.; Hsin, H.-K.; Chang, E.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 8 | 0 | |
14 | 2013 | New ping-pong scheduling for low-latency EMD engine design in Hilbert-Huang transform | Shen, W.-C.; Jen, H.-I.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems II: Express Briefs | 19 | 12 | |
15 | 2013 | Securing M2M with post-quantum public-key cryptography | Shih, J.-R.; Hu, Y.; Hsiao, M.-C.; Chen, M.-S.; Shen, W.-C.; Yang, B.-Y.; Wu, A.-Y.; Cheng, C.-M.; CHEN-MOU CHENG ; AN-YEU(ANDY) WU | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | 20 | 16 | |
16 | 2012 | Path-diversity-aware adaptive routing in network-on-chip systems | Kuo, Y.-H.; Tsai, P.-A.; Ho, H.-P.; Chang, E.-J.; Hsin, H.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE 6th International Symposium on Embedded Multicore SoCs, MCSoC 2012 | 18 | 0 | |
17 | 2012 | Traffic-balanced topology-aware multiple routing adjustment for throttled 3D NoC systems | Chen, K.-C.; Lin, S.-Y.; Hung, H.-S.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 13 | 0 | |
18 | 2012 | Coherent image herding of inhomogeneous motion compensation for synthetic transmit aperture in ultrasound image | Chen, Y.-H.; Ho, K.-Y.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 2 | 0 | |
19 | 2012 | Motion artifact elimination algorithm and architecture for eigen-based clutter filter in color doppler processing | Chen, Y.-H.; Liu, Z.-L.; Lee, I.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | International Journal of Electrical Engineering | |||
20 | 2012 | Iterative superlinear-convergence SVD beamforming algorithm and VLSI architecture for MIMO-OFDM systems | Zhan, C.-Z.; Chen, Y.-L.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Signal Processing | 33 | 33 | |
21 | 2012 | ACO-based Deadlock-Aware fully-adaptive routing in Network-on-Chip systems | Su, K.-Y.; Hsin, H.-K.; Chang, E.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 5 | 0 | |
22 | 2012 | A low-complexity grouping FFT-based codebook searching algorithm in LTE system | Lin, Y.-H.; Zhan, C.-Z.; Chu, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 1 | 0 | |
23 | 2012 | Foreword | Wu, A.-Y.; Wang, L.-C.; AN-YEU(ANDY) WU | 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 | 0 | 0 | |
24 | 2012 | Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems | Chen, K.-C.; Chih-Hao; Lin, S.-Y.; Hung, H.-S.; Wu, A.-Y.; AN-YEU(ANDY) WU | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 | 7 | 0 | |
25 | 2011 | Parallel architecture core (PAC)-the first multicore application processor SoC in Taiwan part I: Hardware architecture & software development tools | Chang, D.C.-W.; Lin, T.-J.; Wu, C.-J.; Lee, J.-K.; Chu, Y.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | Journal of Signal Processing Systems | 13 | 6 | |
26 | 2011 | Traffic-and thermal-aware routing for throttled three-dimensional Network-on-Chip systems | Lin, S.-Y.; Yin, T.-C.; Wang, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 | 46 | 0 | |
27 | 2011 | Multi-Pheromone ACO-based routing in Network-on-Chip system inspired by economic phenomenon | Hsin, H.-K.; Chang, E.-J.; Chao, C.-H.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | International System on Chip Conference | 3 | 0 | |
28 | 2011 | A 0.16nJ/bit/iteration 3.38mm 2 turbo decoder chip for WiMAX/LTE standards | Lin, C.-H.; Chen, C.-Y.; Chang, E.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2011 International Symposium on Integrated Circuits | 9 | 0 | |
29 | 2011 | Parallel architecture core (PAC)-the first multicore application processor SoC in Taiwan part II: Application programming | Chen, J.-M.; Liu, C.-N.; Yang, J.-K.; Tseng, S.-Y.; Shih, W.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU | Journal of Signal Processing Systems | 4 | 3 | |
30 | 2011 | Adaptive thresholding incorporating temporal and spatial information with eigen-based clutter filter for color Doppler processing in ultrasonic systems | Zhan, C.-Z.; Liu, Z.-L.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011 | 4 | 0 | |
31 | 2011 | Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systems | Chao, C.-H.; Yin, T.-C.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | International System on Chip Conference | 21 | 0 | |
32 | 2011 | Area-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding | Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 45 | 34 | |
33 | 2011 | Design of transport layer assisted routing for thermal-aware 3D Network-on-Chip | Yin, T.-C.; Chao, C.-H.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | APSIPA ASC 2011 - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference 2011 | |||
34 | 2010 | A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system | Chen, Y.-L.; Jheng, T.-J.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU | ESSCIRC 2010 - 36th European Solid State Circuits Conference | 0 | 0 | |
35 | 2010 | ACO-based cascaded adaptive routing for traffic balancing in NoC systems | Chang, E.-J.; Chao, C.-H.; Jheng, K.-Y.; Hsin, H.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU | 1st International Conference on Green Circuits and Systems | 16 | 0 | |
36 | 2010 | A two-cycle lock-in time ADPLL design based on a frequency estimation algorithm | Wu, C.-T.; Shen, W.-C.; Wang, W.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems II: Express Briefs | 48 | 40 | |
37 | 2010 | Efficient parallelized particle filter design on CUDA | Chao, M.-A.; Chu, C.-Y.; Chao, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 33 | 0 | |
38 | 2010 | Chairs' message | Bhattacharyya, S.; Janneck, J.; Chen, Y.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
39 | 2010 | Generalized pipelined Tomlinson - Harashima precoder design methodology with build-in arbitrary speed-up factors | Chen, Y.-L.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Signal Processing | 4 | 4 | |
40 | 2010 | Regional ACO-based routing for load-balancing in NoC systems | Hsin, H.-K.; Chang, E.-J.; Chao, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2nd World Congress on Nature and Biologically Inspired Computing, NaBIC 2010 | 20 | 0 | |
41 | 2010 | Joint-decision adaptive clutter filter and motion-tracking adaptive persistence for color doppler processing in ultrasonic systems | Chang, K.-T.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 7 | 0 | |
42 | 2010 | Cost-effective constrained particle filter for indoor localization | Chao, C.-H.; Chu, C.-Y.; Chao, M.-A.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
43 | 2010 | Traffic- and thermal-aware run-time thermal management scheme for 3D NoC systems | Chao, C.-H.; Jheng, K.-Y.; Wang, H.-Y.; Wu, J.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU | NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip | 139 | 0 | |
44 | 2010 | Traffic-thermal mutual-coupling co-simulation platform for three-dimensional network-on-chip | Jheng, K.-Y.; Chao, C.-H.; Wang, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 | 92 | 0 | |
45 | 2010 | Multi-prediction particle filter for effcient memory utilization | Chu, C.-Y.; Chao, C.-H.; Chao, M.-A.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
46 | 2009 | Welcome message from An-Yeu Wu, conference co-chair | Wu, A.-Y.; AN-YEU(ANDY) WU | IMPACT Conference 2009 International 3D IC Conference - Proceedings | 0 | 0 | |
47 | 2009 | A scalable built-in self-test/self-diagnosis architecture for 2D-mesh based chip multiprocessor systems | Lin, S.-Y.; Hsu, C.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 7 | 0 | |
48 | 2009 | High-convergence-speed low-computation-complexity SVD algorithm for MIMO-OFDM systems | Zhan, C.-Z.; Jheng, K.-Y.; Chen, Y.-L.; Jheng, T.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 | 10 | 0 | |
49 | 2009 | Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder | Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; Tsai, T.-H.; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems I: Regular Papers | 42 | 29 | |
50 | 2009 | A real-time programmable LDPC decoder chip for arbitrary QC-LDPC parity check matrices | Shih, X.-Y.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 | 9 | 0 | |
51 | 2009 | Multilevel LINC system designs for power efficiency enhancement of transmitters | Jheng, K.-Y.; Chen, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Journal on Selected Topics in Signal Processing | 33 | 27 | |
52 | 2009 | A triple-mode LDPC decoder design for IEEE 802.11n system | Chao, M.-A.; Wen, J.-Y.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 3 | 0 | |
53 | 2009 | A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications | Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | Asia and South Pacific Design Automation Conference, ASP-DAC | 1 | 0 | |
54 | 2009 | A channel-adaptive early termination strategy for LDPC decoders | Chen, Y.-H.; Chen, Y.-J.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 9 | 0 | |
55 | 2009 | PAC Duo SoC performance analysis with ESL design methodology | Chuang, I.-Y.; Chang, C.-W.; Fan, T.-Y.; Yeh, J.-C.; Ji, K.-M.; Ma, J.-L.; Wu, A.-Y.; Lin, S.-Y.; AN-YEU(ANDY) WU | ASICON 2009 - 8th IEEE International Conference on ASIC | 4 | 0 | |
56 | 2008 | Low-power traceback MAP decoding for double-binary convolutional turbo decoder | Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 2 | 0 | |
57 | 2008 | A universal look-ahead algorithm for pipelining IIR filters | Chen, Y.-L.; Chen, C.-Y.; Jheng, K.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2008 International Symposium on VLSI Design, Automation, and Test | 2 | 0 | |
58 | 2008 | Traffic-balanced routing algorithm for irregular mesh-based on-chip networks | Lin, S.-Y.; Huang, C.-H.; Chao, C.-H.; Huang, K.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Computers | 40 | 29 | |
59 | 2008 | High-throughput dual-mode single/double binary map processor design for wireless wan | Chen, C.-Y.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 3 | 0 | |
60 | 2008 | Overview of ITRI PAC project - From VLIW DSP processor to multicore computing platform | Lin, T.-J.; Liu, C.-N.; Tseng, S.-Y.; Chu, Y.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT | 46 | 0 | |
61 | 2008 | Power efficient low latency survivor memory architecture for viterbi decoder | Chu, C.-Y.; Huang, Y.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT | 10 | 0 | |
62 | 2008 | Traffic-Balanced IP Mapping Algorithm for 2D-mesh on-chip-networks | Lin, T.-J.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 3 | 0 | |
63 | 2008 | Design and analysis of isolated noise-tolerant (INT) technique in dynamic CMOS circuits | Wey, I.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 7 | 3 | |
64 | 2008 | Location-constrained particle filter for rssi-based indoor human positioning and tracking system | Chao, C.-H.; Chu, N.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 14 | 0 | |
65 | 2008 | Energy-effective design & implementation of an embedded VLIW DSP | Hsieh, T.-W.; Hsiao, P.-C.; Liao, C.-Y.; Hsieh, H.-C.; Lin, H.-L.; Lin, T.-J.; Chu, Y.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2008 International SoC Design Conference, ISOCC 2008 | 10 | 0 | |
66 | 2008 | High-throughput 12-mode CTC decoder for WiMAX standard | Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT | 10 | 0 | |
67 | 2008 | High-performance scheduling algorithm for partially parallel LDPC decoder | Zhan, C.-Z.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | 4 | 0 | |
68 | 2008 | A 7.39mm2 76mw (1944, 972) LDPC decoder chip for IEEE 802.11n applications | Shih, X.-Y.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 | 12 | 0 | |
69 | 2008 | Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system | Chen, Y.-L.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 1 | 0 | |
70 | 2008 | An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on Belief Propagation | Rao, H.; Chen, J.; Zhao, V.H.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 2 | 0 | |
71 | 2007 | A new binomial mapping and optimization algorithm for reduced-complexity mesh-based on-chip network | Shen, W.-T.; Chao, C.-H.; Lien, Y.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU | NOCS 2007: First International Symposium on Networks-on-Chip | 78 | 0 | |
72 | 2007 | Dynamic channel flow control of networks-on-chip systems for high buffer efficiency | Wu, S.-T.; Chao, C.-H.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 8 | 0 | |
73 | 2007 | A power-aware reconfigurable rendering engine design with 453MPixels/s, 16.4MTriangles/s performance | Chao, C.-H.; Kuo, Y.-L.; Wu, A.-Y.; Chien, W.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
74 | 2007 | Ensemble dependent matrix methodology for probabilistic-based fault-tolerant nanoscale circuit design | Rao, H.; Chen, J.; Yu, C.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 7 | 0 | |
75 | 2007 | Multilevel LINC system design for wireless transmitters | Chen, Y.-J.; Jheng, K.-Y.; Wu, A.-Y.; Tsao, H.-W.; Tzeng, B.; HEN-WAI TSAO ; AN-YEU(ANDY) WU | 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 | 27 | 0 | |
76 | 2007 | A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement | Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2007 IEEE Asian Solid-State Circuits Conference | 3 | 0 | |
77 | 2007 | On the new stopping criteria of iterative turbo decoding by using decoding threshold | Li, F.-M.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Signal Processing | 40 | 34 | |
78 | 2007 | Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules | Ye, J.-J.; Chen, Y.-G.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 1 | 0 | |
79 | 2007 | A 19-mode 8.29mm2 52-mW LDPC decoder chip for IEEE 802.16e system | Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Symposium on VLSI Circuits | 17 | 0 | |
80 | 2007 | Robust packet detector based automatic gain control algorithm for OFDM-based ultra-wideband systems | Chu, N.-Y.; Lai, J.-T.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 4 | 0 | |
81 | 2007 | On the fixed-point properties of mixed-scaling-rotation cordic algorithm | Yu, C.-L.; Yu, T.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 2 | 0 | |
82 | 2007 | A clock-fault tolerant architecture and circuit for reliable nanoelectronics system | Ang, W.T.; Rao, H.F.; Yu, C.; Liu, J.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; Chen, J.; AN-YEU(ANDY) WU | 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007 | 6 | 0 | |
83 | 2007 | Multilevel LINC system design for power efficiency enhancement | Jheng, K.-Y.; Chen, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 7 | 0 | |
84 | 2006 | A Shortened Impulse Response Filter (SIRF) scheme for cost-effective echo canceller design of 10GBase-T ethernet system | Hsu, M.-F.; Chen, Y.-L.; Jheng, K.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation | 4 | 0 | |
85 | 2006 | Rapid IP design of variable-length cached-FFT processor for OFDM-based communication systems | Lee, Y.-H.; Yu, T.-H.; Huang, K.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS | 14 | 0 | |
86 | 2006 | DSP engine design for LINC wireless transmitter systems | Jheng, K.-Y.; Wang, Y.-C.; Wu, A.-Y.; Tsao, H.-W.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
87 | 2006 | A robust band-tracking packet detector (BT-PD) in OFDM-based ultra-wideband systems | Lai, J.-T.; Chu, N.-Y.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation | 3 | 0 | |
88 | 2006 | A new noise-tolerant dynamic circuit design with enhanced PDP performance under low SNR environment | Chen, Y.-G.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2006 IEEE Asian Solid-State Circuits Conference | 1 | 0 | |
89 | 2006 | A low cost packet detector in OFDM-based ultra-wideband systems | Lai, J.-T.; Chu, N.-Y.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation | 2 | 0 | |
90 | 2006 | On-line MSR-cordic VLSI architecture with applications to cost-efficient rotation-based adaptive filtering systems | Yu, T.-H.; Yu, C.-L.; Jheng, K.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS | 1 | 0 | |
91 | 2006 | A triple-mode MAP/VA IP design for advanced wireless communication systems | Lin, C.-H.; Li, F.-M.; Shi, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2005 IEEE Asian Solid-State Circuits Conference | 0 | 0 | |
92 | 2006 | Ultra low-cost 3.2Gb/s optical-rate reed solomon decoder IC design | Hsu, H.-Y.; Yeo, J.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005 | 1 | 0 | |
93 | 2006 | A new early termination scheme of iterative turbo decoding using decoding threshold | Li, F.-M.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation | 2 | 0 | |
94 | 2006 | A 0.18μm probabilistic-based noise-tolerate circuit design and implementation with 28.7dB noise-immunity improvement | Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 | 22 | 0 | |
95 | 2006 | High-performance VLSI architecture of decision feedback equalizer for gigabit systems | Lin, C.-H.; Wu, A.-Y.; Li, F.-M.; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems II: Express Briefs | 22 | 18 | |
96 | 2005 | Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture | Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Signal Processing | 5 | 4 | |
97 | 2005 | Low cost decision feedback equalizer (DFE) design for giga-bit systems | Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | 2 | 0 | |
98 | 2005 | Digital signal processing engine design for polar transmitter in wireless communication systems | Ko, H.-Y.; Wang, Y.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 3 | 0 | |
99 | 2005 | A scalable DCO design for portable ADPLL designs | Wu, C.-T.; Wang, W.; Wey, I.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 18 | 0 | |
100 | 2005 | A memory-reduced Log-MAP kernel for turbo decoder | Tsai, T.-H.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 9 | 0 | |
101 | 2005 | A DVB-T baseband demodulator design based on multimode silicon IPs | Jheng, K.-Y.; Wu, T.-H.; Wang, Y.-C.; Yeo, J.-C.; Cho, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test | 3 | 0 | |
102 | 2005 | Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications | Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems I: Regular Papers | 67 | 50 | |
103 | 2005 | A high-speed scalable shift-register based on-chip serial communication design for SoC applications | Wey, I.-C.; Chen, Y.-G.; Wu, C.-T.; Wang, W.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2005 PhD Research in Microelectronics and Electronics | 0 | 0 | |
104 | 2005 | A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications | Wey, I.-C.; Chang, L.-H.; Chen, Y.-G.; Chang, S.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 5 | 0 | |
105 | 2004 | Multiplierless multirate decimator / interpolator module generator | Jou, S.-J.; Jheng, K.-Y.; Chen, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | |||
106 | 2004 | High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme | Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; AN-YEU(ANDY) WU | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 3 | 3 | |
107 | 2004 | Robust decision feedback equalizer design using soft-threshold-based multi-layer detection scheme | Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
108 | 2004 | A fast and power-saving self-timed manchester carry-bypass adder for booth multiplier-accumulator design | Wey, I.-C.; Chow, H.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | |||
109 | 2004 | Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique | Yang, M.-D.; Wu, A.-Y.; Lai, J.-T.; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | 3 | 3 | |
110 | 2004 | A design flow for multiplierless linear-phase fir filters: From system specification to verilog code | Jheng, K.-Y.; Jou, S.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
111 | 2003 | Dual-mode convolutional/SOVA based turbo code decoder VLSI design for wireless communication systems | Chen, P.-H.; Kai-Huang; Hsueh, N.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International SOC Conference, SOCC 2003 | 2 | 0 | |
112 | 2003 | Implementation of a programmable 64?2048-point FFT/IFFT processor for OFDM-based communication systems | Kuo, J.-C.; Wen, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
113 | 2003 | A novel multipath matrix algorithm for exact room response identification in stereo echo cancellation | Lai, J.-T.; Wu, A.-Y.; Yeh, C.-C.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 1 | 0 | |
114 | 2003 | Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) algorithm and architecture for scaling-free high-perforance rotatioal operations | Lin, Z.-X.; Wu, A.-Y.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
115 | 2002 | A unified view for vector rotational CORDIC algorithms and architectures based on angle quantization approach | Wu, A.-Y.; Wu, C.-S.; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications | 27 | 26 | |
116 | 2002 | VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems | Hsu, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 | 16 | 0 | |
117 | 2001 | A novel Trellis-based searching scheme for EEAS-based CORDIC algorithm | Wu, C.-S.; Wu, A.-Y.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
118 | 2001 | Cost-efficient multiplier-less FIR filter structure based on modified decor transformation | Lee, I.-H.; Wu, C.-S.; Wu, A.-Y.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
119 | 2001 | Cost-efficient multiplier-less FIR filter structure based on modified decor transformation | Lee, I.-H.; Wu, C.-S.; Wu, A.-Y.; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings | 4 | 0 | |
120 | 2001 | An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter | Yu, C.-L.; Wu, A.-Y.; AN-YEU(ANDY) WU | Materials Research Society Symposium |